The CPUfreq HW present in some Mediatek chipsets offloads the steps necessary for changing the frequency of CPUs.
The driver implements the cpufreq driver interface for this hardware engine.
This patch depends on MT6779 DTS patch[1] submitted by Hanks Chen.
From v7 to v8, there are three more patches based on patchset[2].
This patchset is about to register power table to Energy model for EAS and thermal usage.
1. EM CPU power table
- Register energy model table for EAS and thermal cooling device usage.
- Read the coresponding LUT for power table.
2. SVS initialization
- The SVS(Smart Voltage Scaling) engine is a hardware which is
used to calculate optimized voltage values for CPU power domain.
DVFS driver could apply those optimized voltage values to reduce power consumption.
- Driver will polling if HW engine is done for SVS initialization.
After that, driver will read power table and register it to EAS.
- CPUs must be in power on state when doing SVS. Use pm_qos to block cpu-idle state for SVS initializing.
3. Cooling device flag
- Add cooling device flag for thermal
[1] https://lkml.org/lkml/2020/8/4/1094
[2] https://lkml.org/lkml/2020/9/23/384
Hector.Yuan (3):
cpufreq: mediatek-hw: Add support for CPUFREQ HW
dt-bindings: arm: cpus: Document 'mediatek,freq-domain' property
dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW
Documentation/devicetree/bindings/arm/cpus.yaml | 6 +
.../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 113 +++++++
drivers/cpufreq/Kconfig.arm | 12 +
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/mediatek-cpufreq-hw.c | 343 ++++++++++++++++++++
5 files changed, 475 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
create mode 100644 drivers/cpufreq/mediatek-cpufreq-hw.c
From: "Hector.Yuan" <[email protected]>
Add devicetree bindings for MediaTek HW driver.
Signed-off-by: Hector.Yuan <[email protected]>
---
.../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 113 ++++++++++++++++++++
1 file changed, 113 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
new file mode 100644
index 0000000..32d2ad4
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek's CPUFREQ Bindings
+
+maintainers:
+ - Hector Yuan <[email protected]>
+
+description:
+ CPUFREQ HW is a hardware engine used by MediaTek
+ SoCs to manage frequency in hardware. It is capable of controlling frequency
+ for multiple clusters.
+
+properties:
+ compatible:
+ const: mediatek,cpufreq-hw
+
+ reg:
+ minItems: 1
+ maxItems: 2
+ description: |
+ Addresses and sizes for the memory of the HW bases in each frequency domain.
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 0>;
+ reg = <0x000>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 0>;
+ reg = <0x100>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 0>;
+ reg = <0x200>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 0>;
+ reg = <0x300>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 1>;
+ reg = <0x400>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 1>;
+ reg = <0x500>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 1>;
+ reg = <0x600>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ mediatek,freq-domain = <&cpufreq_hw 1>;
+ reg = <0x700>;
+ };
+ };
+
+ /* ... */
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpufreq_hw: cpufreq@11bc00 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x11bc10 0 0x8c>,
+ <0 0x11bca0 0 0x8c>;
+ };
+ };
--
1.7.9.5
From: "Hector.Yuan" <[email protected]>
Add devicetree documentation for 'mediatek,freq-domain' property specific
to Mediatek CPUs. This property is used to reference the CPUFREQ node
along with the domain id.
Signed-off-by: Hector.Yuan <[email protected]>
---
Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 1222bf1..e995b26 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -255,6 +255,12 @@ properties:
where voltage is in V, frequency is in MHz.
+ mediatek,freq-domain:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ description:
+ CPUs supporting freq-domain must set their "mediatek,freq-domain" property
+ with phandle to a cpufreq_hw node followed by the domain id.
+
power-domains:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
description:
--
1.7.9.5
On Mon, Oct 26, 2020 at 04:19:08PM +0800, Hector Yuan wrote:
> From: "Hector.Yuan" <[email protected]>
>
> Add devicetree documentation for 'mediatek,freq-domain' property specific
> to Mediatek CPUs. This property is used to reference the CPUFREQ node
> along with the domain id.
>
> Signed-off-by: Hector.Yuan <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> index 1222bf1..e995b26 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> @@ -255,6 +255,12 @@ properties:
>
> where voltage is in V, frequency is in MHz.
>
> + mediatek,freq-domain:
> + $ref: '/schemas/types.yaml#/definitions/phandle-array'
> + description:
> + CPUs supporting freq-domain must set their "mediatek,freq-domain" property
> + with phandle to a cpufreq_hw node followed by the domain id.
This needs to be a common binding shared with SCMI domains.
> +
> power-domains:
> $ref: '/schemas/types.yaml#/definitions/phandle-array'
> description:
> --
> 1.7.9.5
On 10/28/20 3:08 PM, Rob Herring wrote:
> On Mon, Oct 26, 2020 at 04:19:08PM +0800, Hector Yuan wrote:
>> From: "Hector.Yuan" <[email protected]>
>>
>> Add devicetree documentation for 'mediatek,freq-domain' property specific
>> to Mediatek CPUs. This property is used to reference the CPUFREQ node
>> along with the domain id.
>>
>> Signed-off-by: Hector.Yuan <[email protected]>
>> ---
>> Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
>> index 1222bf1..e995b26 100644
>> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
>> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
>> @@ -255,6 +255,12 @@ properties:
>>
>> where voltage is in V, frequency is in MHz.
>>
>> + mediatek,freq-domain:
>> + $ref: '/schemas/types.yaml#/definitions/phandle-array'
>> + description:
>> + CPUs supporting freq-domain must set their "mediatek,freq-domain" property
>> + with phandle to a cpufreq_hw node followed by the domain id.
>
> This needs to be a common binding shared with SCMI domains.
Would it be accurate to create a new binding file:
Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.txt
?
There is already cpufreq-qcom-hw.txt with 'qcom,freq-domain'
and analogous purpose.
Regards,
Lukasz
On Thu, Nov 19, 2020 at 03:23:20PM +0000, Lukasz Luba wrote:
>
>
> On 10/28/20 3:08 PM, Rob Herring wrote:
> > On Mon, Oct 26, 2020 at 04:19:08PM +0800, Hector Yuan wrote:
> > > From: "Hector.Yuan" <[email protected]>
> > >
> > > Add devicetree documentation for 'mediatek,freq-domain' property specific
> > > to Mediatek CPUs. This property is used to reference the CPUFREQ node
> > > along with the domain id.
> > >
> > > Signed-off-by: Hector.Yuan <[email protected]>
> > > ---
> > > Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
> > > 1 file changed, 6 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> > > index 1222bf1..e995b26 100644
> > > --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> > > +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> > > @@ -255,6 +255,12 @@ properties:
> > > where voltage is in V, frequency is in MHz.
> > > + mediatek,freq-domain:
> > > + $ref: '/schemas/types.yaml#/definitions/phandle-array'
> > > + description:
> > > + CPUs supporting freq-domain must set their "mediatek,freq-domain" property
> > > + with phandle to a cpufreq_hw node followed by the domain id.
> >
> > This needs to be a common binding shared with SCMI domains.
>
> Would it be accurate to create a new binding file:
> Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.txt
> ?
>
Nope, Rob already asked to unify all such bindings and generalise it.
Here is my attempt[1] and this must just use it or help to enhance that
in order to make use of that binding.
--
Regards,
Sudeep
[1] https://lore.kernel.org/lkml/[email protected]
On 11/19/20 5:13 PM, Sudeep Holla wrote:
> On Thu, Nov 19, 2020 at 03:23:20PM +0000, Lukasz Luba wrote:
>>
>>
>> On 10/28/20 3:08 PM, Rob Herring wrote:
>>> On Mon, Oct 26, 2020 at 04:19:08PM +0800, Hector Yuan wrote:
>>>> From: "Hector.Yuan" <[email protected]>
>>>>
>>>> Add devicetree documentation for 'mediatek,freq-domain' property specific
>>>> to Mediatek CPUs. This property is used to reference the CPUFREQ node
>>>> along with the domain id.
>>>>
>>>> Signed-off-by: Hector.Yuan <[email protected]>
>>>> ---
>>>> Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
>>>> 1 file changed, 6 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
>>>> index 1222bf1..e995b26 100644
>>>> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
>>>> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
>>>> @@ -255,6 +255,12 @@ properties:
>>>> where voltage is in V, frequency is in MHz.
>>>> + mediatek,freq-domain:
>>>> + $ref: '/schemas/types.yaml#/definitions/phandle-array'
>>>> + description:
>>>> + CPUs supporting freq-domain must set their "mediatek,freq-domain" property
>>>> + with phandle to a cpufreq_hw node followed by the domain id.
>>>
>>> This needs to be a common binding shared with SCMI domains.
>>
>> Would it be accurate to create a new binding file:
>> Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.txt
>> ?
>>
>
> Nope, Rob already asked to unify all such bindings and generalise it.
> Here is my attempt[1] and this must just use it or help to enhance that
> in order to make use of that binding.
>
That's great. Thank you for the information.
Regards,
Lukasz