Hi,
This is the v3 series to add some DRM bridge drivers support
for i.MX8qm/qxp SoCs.
The bridges may chain one by one to form display pipes to support
LVDS displays. The relevant display controller is DPU embedded in
i.MX8qm/qxp SoCs.
The DPU KMS driver can be found at:
https://www.spinics.net/lists/arm-kernel/msg871357.html
This series supports the following display pipes:
1) i.MX8qxp:
prefetch eng -> DPU -> pixel combiner -> pixel link ->
pixel link to DPI(PXL2DPI) -> LVDS display bridge(LDB)
2) i.MX8qm:
prefetch eng -> DPU -> pixel combiner -> pixel link -> LVDS display bridge(LDB)
Patch 1/14 adds LVDS PHY configuration options, which has already been sent
with the following series to add Mixel combo PHY found in i.MX8qxp:
https://www.spinics.net/lists/arm-kernel/msg862560.html
Patch 2/14 and 3/14 add bus formats used by PXL2DPI.
Patch 4/14 ~ 13/14 add drm bridge drivers and dt-bindings support for the bridges.
Patch 14/14 updates MAINTAINERS.
I've tested this series with a koe,tx26d202vm0bwa dual link LVDS panel and
a LVDS to HDMI bridge(with a downstream drm bridge driver).
Welcome comments, thanks.
v2->v3:
* Drop 'fsl,syscon' DT properties from fsl,imx8qxp-ldb.yaml and
fsl,imx8qxp-pxl2dpi.yaml. (Rob)
* Mention the CSR module controls LDB and PXL2DPI in fsl,imx8qxp-ldb.yaml and
fsl,imx8qxp-pxl2dpi.yaml.
* Call syscon_node_to_regmap() to get regmaps from LDB bridge helper driver
and PXL2DPI bridger driver instead of syscon_regmap_lookup_by_phandle().
* Drop two macros from pixel link bridge driver which help define functions
and define them directly.
* Properly disable all pixel link controls to POR value by calling
imx8qxp_pixel_link_disable_all_controls() from
imx8qxp_pixel_link_bridge_probe().
* Add Rob's R-b tags on patch 4/14 and 6/14.
v1->v2:
* Rebase the series upon the latest drm-misc-next branch(5.11-rc2 based).
* Use graph schema in the dt-bindings of the bridges. (Laurent)
* Require all four pixel link output ports in fsl,imx8qxp-pixel-link.yaml.
(Laurent)
* Side note i.MX8qm/qxp LDB official name 'pixel mapper' in fsl,imx8qxp-ldb.yaml.
(Laurent)
* Mention pixel link is accessed via SCU firmware in fsl,imx8qxp-pixel-link.yaml.
(Rob)
* Use enum instead of oneOf + const for the reg property of pixel combiner
channels in fsl,imx8qxp-pixel-combiner.yaml. (Rob)
* Rewrite the function to find the next bridge in pixel link bridge driver
by properly using OF APIs and dropping unnecessary DT validation. (Rob)
* Drop unnecessary port availability check in i.MX8qxp pixel link to DPI
bridge driver.
* Drop unnecessary DT validation from i.MX8qxp LDB bridge driver.
* Use of_graph_get_endpoint_by_regs() and of_graph_get_remote_endpoint() to
get the input remote endpoint in imx8qxp_ldb_set_di_id() of i.MX8qxp LDB
bridge driver.
* Avoid using companion_port OF node after putting it in
imx8qxp_ldb_parse_dt_companion() of i.MX8qxp LDB bridge driver.
* Drop unnecessary check for maximum available LDB channels from
i.MX8qm LDB bridge driver.
* Mention i.MX8qm/qxp LDB official name 'pixel mapper' in i.MX8qm/qxp LDB
bridge drivers and Kconfig help messages.
Liu Ying (14):
phy: Add LVDS configuration options
media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner
media: docs: Add some RGB bus formats for i.MX8qm/qxp pixel combiner
dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding
drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support
dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link
binding
drm/bridge: imx: Add i.MX8qm/qxp display pixel link support
dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding
drm/bridge: imx: Add i.MX8qxp pixel link to DPI support
drm/bridge: imx: Add LDB driver helper support
dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge
binding
drm/bridge: imx: Add LDB support for i.MX8qxp
drm/bridge: imx: Add LDB support for i.MX8qm
MAINTAINERS: add maintainer for DRM bridge drivers for i.MX SoCs
.../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 173 +++++
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 144 +++++
.../display/bridge/fsl,imx8qxp-pixel-link.yaml | 106 +++
.../display/bridge/fsl,imx8qxp-pxl2dpi.yaml | 102 +++
.../userspace-api/media/v4l/subdev-formats.rst | 156 +++++
MAINTAINERS | 10 +
drivers/gpu/drm/bridge/Kconfig | 2 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/imx/Kconfig | 52 ++
drivers/gpu/drm/bridge/imx/Makefile | 6 +
drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 248 +++++++
drivers/gpu/drm/bridge/imx/imx8qm-ldb.c | 585 +++++++++++++++++
drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c | 719 +++++++++++++++++++++
.../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c | 452 +++++++++++++
drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 426 ++++++++++++
drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c | 488 ++++++++++++++
include/drm/bridge/imx_ldb_helper.h | 98 +++
include/linux/phy/phy-lvds.h | 48 ++
include/linux/phy/phy.h | 4 +
include/uapi/linux/media-bus-format.h | 6 +-
20 files changed, 3825 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
create mode 100644 drivers/gpu/drm/bridge/imx/Kconfig
create mode 100644 drivers/gpu/drm/bridge/imx/Makefile
create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qm-ldb.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
create mode 100644 include/drm/bridge/imx_ldb_helper.h
create mode 100644 include/linux/phy/phy-lvds.h
--
2.7.4
This patch allows LVDS PHYs to be configured through
the generic functions and through a custom structure
added to the generic union.
The parameters added here are based on common LVDS PHY
implementation practices. The set of parameters
should cover all potential users.
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: NXP Linux Team <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
v2->v3:
* No change.
v1->v2:
* No change.
include/linux/phy/phy-lvds.h | 48 ++++++++++++++++++++++++++++++++++++++++++++
include/linux/phy/phy.h | 4 ++++
2 files changed, 52 insertions(+)
create mode 100644 include/linux/phy/phy-lvds.h
diff --git a/include/linux/phy/phy-lvds.h b/include/linux/phy/phy-lvds.h
new file mode 100644
index 00000000..1b5b9d6
--- /dev/null
+++ b/include/linux/phy/phy-lvds.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __PHY_LVDS_H_
+#define __PHY_LVDS_H_
+
+/**
+ * struct phy_configure_opts_lvds - LVDS configuration set
+ *
+ * This structure is used to represent the configuration state of a
+ * LVDS phy.
+ */
+struct phy_configure_opts_lvds {
+ /**
+ * @bits_per_lane_and_dclk_cycle:
+ *
+ * Number of bits per data lane and differential clock cycle.
+ */
+ unsigned int bits_per_lane_and_dclk_cycle;
+
+ /**
+ * @differential_clk_rate:
+ *
+ * Clock rate, in Hertz, of the LVDS differential clock.
+ */
+ unsigned long differential_clk_rate;
+
+ /**
+ * @lanes:
+ *
+ * Number of active, consecutive, data lanes, starting from
+ * lane 0, used for the transmissions.
+ */
+ unsigned int lanes;
+
+ /**
+ * @is_slave:
+ *
+ * Boolean, true if the phy is a slave which works together
+ * with a master phy to support dual link transmission,
+ * otherwise a regular phy or a master phy.
+ */
+ bool is_slave;
+};
+
+#endif /* __PHY_LVDS_H_ */
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index e435bdb..d450b44 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -17,6 +17,7 @@
#include <linux/regulator/consumer.h>
#include <linux/phy/phy-dp.h>
+#include <linux/phy/phy-lvds.h>
#include <linux/phy/phy-mipi-dphy.h>
struct phy;
@@ -51,10 +52,13 @@ enum phy_mode {
* the MIPI_DPHY phy mode.
* @dp: Configuration set applicable for phys supporting
* the DisplayPort protocol.
+ * @lvds: Configuration set applicable for phys supporting
+ * the LVDS phy mode.
*/
union phy_configure_opts {
struct phy_configure_opts_mipi_dphy mipi_dphy;
struct phy_configure_opts_dp dp;
+ struct phy_configure_opts_lvds lvds;
};
/**
--
2.7.4
This patch adds RGB666_1X30_CPADLO, RGB888_1X30_CPADLO, RGB666_1X36_CPADLO
and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp pixel combiner.
The RGB pixels with padding low per component are transmitted on a 30-bit
input bus(10-bit per component) from a display controller or a 36-bit
output bus(12-bit per component) to a pixel link.
Signed-off-by: Liu Ying <[email protected]>
---
v2->v3:
* No change.
v1->v2:
* No change.
include/uapi/linux/media-bus-format.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h
index 0dfc11e..ec3323d 100644
--- a/include/uapi/linux/media-bus-format.h
+++ b/include/uapi/linux/media-bus-format.h
@@ -34,7 +34,7 @@
#define MEDIA_BUS_FMT_FIXED 0x0001
-/* RGB - next is 0x101e */
+/* RGB - next is 0x1022 */
#define MEDIA_BUS_FMT_RGB444_1X12 0x1016
#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
@@ -59,9 +59,13 @@
#define MEDIA_BUS_FMT_RGB888_3X8_DELTA 0x101d
#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011
#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012
+#define MEDIA_BUS_FMT_RGB666_1X30_CPADLO 0x101e
+#define MEDIA_BUS_FMT_RGB888_1X30_CPADLO 0x101f
#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d
#define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f
#define MEDIA_BUS_FMT_RGB101010_1X30 0x1018
+#define MEDIA_BUS_FMT_RGB666_1X36_CPADLO 0x1020
+#define MEDIA_BUS_FMT_RGB888_1X36_CPADLO 0x1021
#define MEDIA_BUS_FMT_RGB121212_1X36 0x1019
#define MEDIA_BUS_FMT_RGB161616_1X48 0x101a
--
2.7.4