From: Vincent Cheng <[email protected]>
This series fixes a race condition that may result in the output clock
not aligned to internal 1 PPS clock.
Part of device initialization is to align the rising edge of output
clocks to the internal rising edge of the 1 PPS clock. If the system
APLL and DPLL are not locked when this alignment occurs, the alignment
fails and a fixed offset between the internal 1 PPS clock and the
output clock occurs.
If a clock is dynamically enabled after power-up, the output clock
also needs to be aligned to the internal 1 PPS clock.
v2:
Suggested by: Richard Cochran <[email protected]>
- Added const to "char * fmt"
- Break unrelated header change into separate patch
Vincent Cheng (3):
ptp: ptp_clockmatrix: Add wait_for_sys_apll_dpll_lock.
ptp: ptp_clockmatrix: Add alignment of 1 PPS to idtcm_perout_enable.
ptp: ptp_clockmatrix: Remove unused header declarations.
drivers/ptp/idt8a340_reg.h | 10 +++++
drivers/ptp/ptp_clockmatrix.c | 92 ++++++++++++++++++++++++++++++++++++++++---
drivers/ptp/ptp_clockmatrix.h | 17 +++++++-
3 files changed, 112 insertions(+), 7 deletions(-)
--
2.7.4
From: Vincent Cheng <[email protected]>
Removed unused header declarations.
Signed-off-by: Vincent Cheng <[email protected]>
---
drivers/ptp/ptp_clockmatrix.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h
index 0233236..fb32327 100644
--- a/drivers/ptp/ptp_clockmatrix.h
+++ b/drivers/ptp/ptp_clockmatrix.h
@@ -15,7 +15,6 @@
#define FW_FILENAME "idtcm.bin"
#define MAX_TOD (4)
#define MAX_PLL (8)
-#define MAX_OUTPUT (12)
#define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)
@@ -138,7 +137,6 @@ struct idtcm_channel {
enum pll_mode pll_mode;
u8 pll;
u16 output_mask;
- u8 output_phase_adj[MAX_OUTPUT][4];
};
struct idtcm {
--
2.7.4