2021-02-18 03:58:45

by Liu Ying

[permalink] [raw]
Subject: [PATCH v4 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs

Hi,

This is the v4 series to add some DRM bridge drivers support
for i.MX8qm/qxp SoCs.

The bridges may chain one by one to form display pipes to support
LVDS displays. The relevant display controller is DPU embedded in
i.MX8qm/qxp SoCs.

The DPU KMS driver can be found at:
https://www.spinics.net/lists/arm-kernel/msg871357.html

This series supports the following display pipes:
1) i.MX8qxp:
prefetch eng -> DPU -> pixel combiner -> pixel link ->
pixel link to DPI(PXL2DPI) -> LVDS display bridge(LDB)

2) i.MX8qm:
prefetch eng -> DPU -> pixel combiner -> pixel link -> LVDS display bridge(LDB)


Patch 1/14 adds LVDS PHY configuration options, which has already been sent
with the following series to add Mixel combo PHY found in i.MX8qxp:
https://www.spinics.net/lists/arm-kernel/msg862560.html

Patch 2/14 and 3/14 add bus formats used by PXL2DPI.

Patch 4/14 ~ 13/14 add drm bridge drivers and dt-bindings support for the bridges.

Patch 14/14 updates MAINTAINERS.


I've tested this series with a koe,tx26d202vm0bwa dual link LVDS panel and
a LVDS to HDMI bridge(with a downstream drm bridge driver).


Welcome comments, thanks.

v3->v4:
* Use 'fsl,sc-resource' DT property to get the SCU resource ID associated with
the PXL2DPI instance instead of using alias ID. (Rob)
* Add Rob's R-b tag on patch 11/14.

v2->v3:
* Drop 'fsl,syscon' DT properties from fsl,imx8qxp-ldb.yaml and
fsl,imx8qxp-pxl2dpi.yaml. (Rob)
* Mention the CSR module controls LDB and PXL2DPI in fsl,imx8qxp-ldb.yaml and
fsl,imx8qxp-pxl2dpi.yaml.
* Call syscon_node_to_regmap() to get regmaps from LDB bridge helper driver
and PXL2DPI bridger driver instead of syscon_regmap_lookup_by_phandle().
* Drop two macros from pixel link bridge driver which help define functions
and define them directly.
* Properly disable all pixel link controls to POR value by calling
imx8qxp_pixel_link_disable_all_controls() from
imx8qxp_pixel_link_bridge_probe().
* Add Rob's R-b tags on patch 4/14 and 6/14.

v1->v2:
* Rebase the series upon the latest drm-misc-next branch(5.11-rc2 based).
* Use graph schema in the dt-bindings of the bridges. (Laurent)
* Require all four pixel link output ports in fsl,imx8qxp-pixel-link.yaml.
(Laurent)
* Side note i.MX8qm/qxp LDB official name 'pixel mapper' in fsl,imx8qxp-ldb.yaml.
(Laurent)
* Mention pixel link is accessed via SCU firmware in fsl,imx8qxp-pixel-link.yaml.
(Rob)
* Use enum instead of oneOf + const for the reg property of pixel combiner
channels in fsl,imx8qxp-pixel-combiner.yaml. (Rob)
* Rewrite the function to find the next bridge in pixel link bridge driver
by properly using OF APIs and dropping unnecessary DT validation. (Rob)
* Drop unnecessary port availability check in i.MX8qxp pixel link to DPI
bridge driver.
* Drop unnecessary DT validation from i.MX8qxp LDB bridge driver.
* Use of_graph_get_endpoint_by_regs() and of_graph_get_remote_endpoint() to
get the input remote endpoint in imx8qxp_ldb_set_di_id() of i.MX8qxp LDB
bridge driver.
* Avoid using companion_port OF node after putting it in
imx8qxp_ldb_parse_dt_companion() of i.MX8qxp LDB bridge driver.
* Drop unnecessary check for maximum available LDB channels from
i.MX8qm LDB bridge driver.
* Mention i.MX8qm/qxp LDB official name 'pixel mapper' in i.MX8qm/qxp LDB
bridge drivers and Kconfig help messages.
Liu Ying (14):
phy: Add LVDS configuration options
media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner
media: docs: Add some RGB bus formats for i.MX8qm/qxp pixel combiner
dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding
drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support
dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link
binding
drm/bridge: imx: Add i.MX8qm/qxp display pixel link support
dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding
drm/bridge: imx: Add i.MX8qxp pixel link to DPI support
drm/bridge: imx: Add LDB driver helper support
dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge
binding
drm/bridge: imx: Add LDB support for i.MX8qxp
drm/bridge: imx: Add LDB support for i.MX8qm
MAINTAINERS: add maintainer for DRM bridge drivers for i.MX SoCs

.../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 173 +++++
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 144 +++++
.../display/bridge/fsl,imx8qxp-pixel-link.yaml | 106 +++
.../display/bridge/fsl,imx8qxp-pxl2dpi.yaml | 108 ++++
.../userspace-api/media/v4l/subdev-formats.rst | 156 +++++
MAINTAINERS | 10 +
drivers/gpu/drm/bridge/Kconfig | 2 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/imx/Kconfig | 52 ++
drivers/gpu/drm/bridge/imx/Makefile | 6 +
drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 248 +++++++
drivers/gpu/drm/bridge/imx/imx8qm-ldb.c | 585 +++++++++++++++++
drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c | 719 +++++++++++++++++++++
.../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c | 452 +++++++++++++
drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 426 ++++++++++++
drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c | 485 ++++++++++++++
include/drm/bridge/imx_ldb_helper.h | 98 +++
include/linux/phy/phy-lvds.h | 48 ++
include/linux/phy/phy.h | 4 +
include/uapi/linux/media-bus-format.h | 6 +-
20 files changed, 3828 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
create mode 100644 drivers/gpu/drm/bridge/imx/Kconfig
create mode 100644 drivers/gpu/drm/bridge/imx/Makefile
create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qm-ldb.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
create mode 100644 include/drm/bridge/imx_ldb_helper.h
create mode 100644 include/linux/phy/phy-lvds.h

--
2.7.4


2021-02-18 03:58:49

by Liu Ying

[permalink] [raw]
Subject: [PATCH v4 02/14] media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner

This patch adds RGB666_1X30_CPADLO, RGB888_1X30_CPADLO, RGB666_1X36_CPADLO
and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp pixel combiner.
The RGB pixels with padding low per component are transmitted on a 30-bit
input bus(10-bit per component) from a display controller or a 36-bit
output bus(12-bit per component) to a pixel link.

Signed-off-by: Liu Ying <[email protected]>
---
v3->v4:
* No change.

v2->v3:
* No change.

v1->v2:
* No change.

include/uapi/linux/media-bus-format.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h
index 0dfc11e..ec3323d 100644
--- a/include/uapi/linux/media-bus-format.h
+++ b/include/uapi/linux/media-bus-format.h
@@ -34,7 +34,7 @@

#define MEDIA_BUS_FMT_FIXED 0x0001

-/* RGB - next is 0x101e */
+/* RGB - next is 0x1022 */
#define MEDIA_BUS_FMT_RGB444_1X12 0x1016
#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
@@ -59,9 +59,13 @@
#define MEDIA_BUS_FMT_RGB888_3X8_DELTA 0x101d
#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011
#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012
+#define MEDIA_BUS_FMT_RGB666_1X30_CPADLO 0x101e
+#define MEDIA_BUS_FMT_RGB888_1X30_CPADLO 0x101f
#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d
#define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f
#define MEDIA_BUS_FMT_RGB101010_1X30 0x1018
+#define MEDIA_BUS_FMT_RGB666_1X36_CPADLO 0x1020
+#define MEDIA_BUS_FMT_RGB888_1X36_CPADLO 0x1021
#define MEDIA_BUS_FMT_RGB121212_1X36 0x1019
#define MEDIA_BUS_FMT_RGB161616_1X48 0x101a

--
2.7.4

2021-02-18 03:59:21

by Liu Ying

[permalink] [raw]
Subject: [PATCH v4 13/14] drm/bridge: imx: Add LDB support for i.MX8qm

This patch adds a drm bridge driver for i.MX8qm LVDS display bridge(LDB)
which is officially named as pixel mapper. The LDB has two channels.
Each of them supports up to 30bpp parallel input color format and can
map the input to VESA or JEIDA standards. The two channels can be used
simultaneously, either in dual mode or split mode. In dual mode, the
two channels output identical data. In split mode, channel0 outputs
odd pixels and channel1 outputs even pixels. This patch supports the
LDB single mode and split mode.

Signed-off-by: Liu Ying <[email protected]>
---
v3->v4:
* No change.

v2->v3:
* No change.

v1->v2:
* Drop unnecessary check for maximum available LDB channels.
* Mention i.MX8qm LDB official name 'pixel mapper' in the bridge driver
and Kconfig help message.

drivers/gpu/drm/bridge/imx/Kconfig | 10 +
drivers/gpu/drm/bridge/imx/Makefile | 1 +
drivers/gpu/drm/bridge/imx/imx8qm-ldb.c | 585 ++++++++++++++++++++++++++++++++
3 files changed, 596 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qm-ldb.c

diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
index 07ad230..290509c 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -6,6 +6,16 @@ config DRM_IMX_LVDS_BRIDGE_HELPER
Helper to support Freescale i.MX LVDS Display Bridge(LDB).
This bridge is embedded in a SoC.

+config DRM_IMX8QM_LDB
+ tristate "Freescale i.MX8QM LVDS display bridge"
+ depends on DRM_IMX_LVDS_BRIDGE_HELPER
+ depends on OF
+ depends on COMMON_CLK
+ select DRM_KMS_HELPER
+ help
+ Choose this to enable the internal LVDS Display Bridge(LDB) found in
+ Freescale i.MX8qm processor. Official name of LDB is pixel mapper.
+
config DRM_IMX8QXP_LDB
tristate "Freescale i.MX8QXP LVDS display bridge"
depends on DRM_IMX_LVDS_BRIDGE_HELPER
diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
index 13160f0..a964efc 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_DRM_IMX_LVDS_BRIDGE_HELPER) += imx-ldb-helper.o
+obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o
obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c b/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c
new file mode 100644
index 00000000..bf0b5ce
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c
@@ -0,0 +1,585 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/phy/phy.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <drm/bridge/imx_ldb_helper.h>
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_connector.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_of.h>
+#include <drm/drm_print.h>
+
+#define LDB_CH0_10BIT_EN (1 << 22)
+#define LDB_CH1_10BIT_EN (1 << 23)
+#define LDB_CH0_DATA_WIDTH_24BIT (1 << 24)
+#define LDB_CH1_DATA_WIDTH_24BIT (1 << 26)
+#define LDB_CH0_DATA_WIDTH_30BIT (2 << 24)
+#define LDB_CH1_DATA_WIDTH_30BIT (2 << 26)
+
+#define SS_CTRL 0x20
+#define CH_HSYNC_M(id) BIT(0 + ((id) * 2))
+#define CH_VSYNC_M(id) BIT(1 + ((id) * 2))
+#define CH_PHSYNC(id) BIT(0 + ((id) * 2))
+#define CH_PVSYNC(id) BIT(1 + ((id) * 2))
+
+#define DRIVER_NAME "imx8qm-ldb"
+
+struct imx8qm_ldb_channel {
+ struct ldb_channel base;
+ struct phy *phy;
+};
+
+struct imx8qm_ldb {
+ struct ldb base;
+ struct device *dev;
+ struct imx8qm_ldb_channel channel[MAX_LDB_CHAN_NUM];
+ struct clk *clk_pixel;
+ struct clk *clk_bypass;
+ int active_chno;
+};
+
+static inline struct imx8qm_ldb_channel *
+base_to_imx8qm_ldb_channel(struct ldb_channel *base)
+{
+ return container_of(base, struct imx8qm_ldb_channel, base);
+}
+
+static inline struct imx8qm_ldb *base_to_imx8qm_ldb(struct ldb *base)
+{
+ return container_of(base, struct imx8qm_ldb, base);
+}
+
+static void imx8qm_ldb_set_phy_cfg(struct imx8qm_ldb *imx8qm_ldb,
+ unsigned long di_clk,
+ bool is_split, bool is_slave,
+ struct phy_configure_opts_lvds *phy_cfg)
+{
+ phy_cfg->bits_per_lane_and_dclk_cycle = 7;
+ phy_cfg->lanes = 4;
+ phy_cfg->differential_clk_rate = is_split ? di_clk / 2 : di_clk;
+ phy_cfg->is_slave = is_slave;
+}
+
+static int imx8qm_ldb_bridge_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch =
+ base_to_imx8qm_ldb_channel(ldb_ch);
+ struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
+ struct drm_display_mode *adj = &crtc_state->adjusted_mode;
+ unsigned long di_clk = adj->clock * 1000;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ union phy_configure_opts opts = { };
+ struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
+ int ret;
+
+ ret = ldb_bridge_atomic_check_helper(bridge, bridge_state,
+ crtc_state, conn_state);
+ if (ret)
+ return ret;
+
+ imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg);
+ ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts);
+ if (ret < 0) {
+ DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev,
+ "failed to validate PHY: %d\n", ret);
+ return ret;
+ }
+
+ if (is_split) {
+ imx8qm_ldb_ch =
+ &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1];
+ imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true,
+ phy_cfg);
+ ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts);
+ if (ret < 0) {
+ DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev,
+ "failed to validate slave PHY: %d\n", ret);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static void
+imx8qm_ldb_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch =
+ base_to_imx8qm_ldb_channel(ldb_ch);
+ struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
+ struct device *dev = imx8qm_ldb->dev;
+ unsigned long di_clk = adjusted_mode->clock * 1000;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ union phy_configure_opts opts = { };
+ struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
+ u32 chno = ldb_ch->chno;
+ int ret;
+
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret);
+
+ ret = phy_init(imx8qm_ldb_ch->phy);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret);
+
+ clk_set_rate(imx8qm_ldb->clk_bypass, di_clk);
+ clk_set_rate(imx8qm_ldb->clk_pixel, di_clk);
+
+ imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg);
+ ret = phy_configure(imx8qm_ldb_ch->phy, &opts);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret);
+
+ if (is_split) {
+ imx8qm_ldb_ch =
+ &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1];
+ imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true,
+ phy_cfg);
+ ret = phy_configure(imx8qm_ldb_ch->phy, &opts);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to configure slave PHY: %d\n",
+ ret);
+ }
+
+ /* input VSYNC signal from pixel link is active low */
+ if (ldb_ch->chno == 0 || is_split)
+ ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
+ if (ldb_ch->chno == 1 || is_split)
+ ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
+
+ switch (ldb_ch->out_bus_format) {
+ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+ if (ldb_ch->chno == 0 || is_split)
+ ldb->ldb_ctrl |= LDB_CH0_DATA_WIDTH_24BIT;
+ if (ldb_ch->chno == 1 || is_split)
+ ldb->ldb_ctrl |= LDB_CH1_DATA_WIDTH_24BIT;
+ break;
+ }
+
+ ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode);
+
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0);
+ else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL,
+ CH_VSYNC_M(chno), CH_PVSYNC(chno));
+
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0);
+ else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL,
+ CH_HSYNC_M(chno), CH_PHSYNC(chno));
+}
+
+static void
+imx8qm_ldb_bridge_atomic_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch =
+ base_to_imx8qm_ldb_channel(ldb_ch);
+ struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
+ struct device *dev = imx8qm_ldb->dev;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ int ret;
+
+ clk_prepare_enable(imx8qm_ldb->clk_pixel);
+ clk_prepare_enable(imx8qm_ldb->clk_bypass);
+
+ /* both DI0 and DI1 connect with pixel link, so ok to use DI0 only */
+ if (ldb_ch->chno == 0 || is_split) {
+ ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
+ ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
+ }
+ if (ldb_ch->chno == 1 || is_split) {
+ ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
+ ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
+ }
+
+ if (is_split) {
+ ret = phy_power_on(imx8qm_ldb->channel[0].phy);
+ if (ret)
+ DRM_DEV_ERROR(dev,
+ "failed to power on channel0 PHY: %d\n",
+ ret);
+
+ ret = phy_power_on(imx8qm_ldb->channel[1].phy);
+ if (ret)
+ DRM_DEV_ERROR(dev,
+ "failed to power on channel1 PHY: %d\n",
+ ret);
+ } else {
+ ret = phy_power_on(imx8qm_ldb_ch->phy);
+ if (ret)
+ DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret);
+ }
+
+ ldb_bridge_enable_helper(bridge);
+}
+
+static void
+imx8qm_ldb_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch =
+ base_to_imx8qm_ldb_channel(ldb_ch);
+ struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
+ struct device *dev = imx8qm_ldb->dev;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ int ret;
+
+ ldb_bridge_disable_helper(bridge);
+
+ if (is_split) {
+ ret = phy_power_off(imx8qm_ldb->channel[0].phy);
+ if (ret)
+ DRM_DEV_ERROR(dev,
+ "failed to power off channel0 PHY: %d\n",
+ ret);
+ ret = phy_power_off(imx8qm_ldb->channel[1].phy);
+ if (ret)
+ DRM_DEV_ERROR(dev,
+ "failed to power off channel1 PHY: %d\n",
+ ret);
+ } else {
+ ret = phy_power_off(imx8qm_ldb_ch->phy);
+ if (ret)
+ DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret);
+ }
+
+ clk_disable_unprepare(imx8qm_ldb->clk_bypass);
+ clk_disable_unprepare(imx8qm_ldb->clk_pixel);
+
+ ret = pm_runtime_put(dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret);
+}
+
+static const u32 imx8qm_ldb_bus_output_fmts[] = {
+ MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
+ MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
+ MEDIA_BUS_FMT_FIXED,
+};
+
+static bool imx8qm_ldb_bus_output_fmt_supported(u32 fmt)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx8qm_ldb_bus_output_fmts); i++) {
+ if (imx8qm_ldb_bus_output_fmts[i] == fmt)
+ return true;
+ }
+
+ return false;
+}
+
+static u32 *
+imx8qm_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ struct drm_display_info *di;
+ const struct drm_format_info *finfo;
+ u32 *input_fmts;
+
+ if (!imx8qm_ldb_bus_output_fmt_supported(output_fmt))
+ return NULL;
+
+ *num_input_fmts = 1;
+
+ input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
+ if (!input_fmts)
+ return NULL;
+
+ switch (output_fmt) {
+ case MEDIA_BUS_FMT_FIXED:
+ di = &conn_state->connector->display_info;
+
+ /*
+ * Look at the first bus format to determine input format.
+ * Default to MEDIA_BUS_FMT_RGB888_1X36_CPADLO, if no match.
+ */
+ if (di->num_bus_formats) {
+ finfo = drm_format_info(di->bus_formats[0]);
+
+ input_fmts[0] = finfo->depth == 18 ?
+ MEDIA_BUS_FMT_RGB666_1X36_CPADLO :
+ MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
+ } else {
+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
+ }
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X36_CPADLO;
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
+ break;
+ default:
+ kfree(input_fmts);
+ input_fmts = NULL;
+ break;
+ }
+
+ return input_fmts;
+}
+
+static u32 *
+imx8qm_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ unsigned int *num_output_fmts)
+{
+ *num_output_fmts = ARRAY_SIZE(imx8qm_ldb_bus_output_fmts);
+ return kmemdup(imx8qm_ldb_bus_output_fmts,
+ sizeof(imx8qm_ldb_bus_output_fmts), GFP_KERNEL);
+}
+
+static enum drm_mode_status
+imx8qm_ldb_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ bool is_single = ldb_channel_is_single_link(ldb_ch);
+
+ if (mode->clock > 300000)
+ return MODE_CLOCK_HIGH;
+
+ if (mode->clock > 150000 && is_single)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static const struct drm_bridge_funcs imx8qm_ldb_bridge_funcs = {
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .mode_valid = imx8qm_ldb_bridge_mode_valid,
+ .attach = ldb_bridge_attach_helper,
+ .atomic_check = imx8qm_ldb_bridge_atomic_check,
+ .mode_set = imx8qm_ldb_bridge_mode_set,
+ .atomic_enable = imx8qm_ldb_bridge_atomic_enable,
+ .atomic_disable = imx8qm_ldb_bridge_atomic_disable,
+ .atomic_get_input_bus_fmts =
+ imx8qm_ldb_bridge_atomic_get_input_bus_fmts,
+ .atomic_get_output_bus_fmts =
+ imx8qm_ldb_bridge_atomic_get_output_bus_fmts,
+};
+
+static int imx8qm_ldb_get_phy(struct imx8qm_ldb *imx8qm_ldb)
+{
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch;
+ struct ldb_channel *ldb_ch;
+ struct device *dev = imx8qm_ldb->dev;
+ int i, ret;
+
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
+ imx8qm_ldb_ch = &imx8qm_ldb->channel[i];
+ ldb_ch = &imx8qm_ldb_ch->base;
+
+ if (!ldb_ch->is_available)
+ continue;
+
+ imx8qm_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np,
+ "lvds_phy");
+ if (IS_ERR(imx8qm_ldb_ch->phy)) {
+ ret = PTR_ERR(imx8qm_ldb_ch->phy);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev,
+ "failed to get channel%d PHY: %d\n",
+ i, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int imx8qm_ldb_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct imx8qm_ldb *imx8qm_ldb;
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch;
+ struct ldb *ldb;
+ struct ldb_channel *ldb_ch;
+ struct device_node *port1, *port2;
+ int pixel_order;
+ int ret, i;
+
+ imx8qm_ldb = devm_kzalloc(dev, sizeof(*imx8qm_ldb), GFP_KERNEL);
+ if (!imx8qm_ldb)
+ return -ENOMEM;
+
+ imx8qm_ldb->clk_pixel = devm_clk_get(dev, "pixel");
+ if (IS_ERR(imx8qm_ldb->clk_pixel)) {
+ ret = PTR_ERR(imx8qm_ldb->clk_pixel);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev,
+ "failed to get pixel clock: %d\n", ret);
+ return ret;
+ }
+
+ imx8qm_ldb->clk_bypass = devm_clk_get(dev, "bypass");
+ if (IS_ERR(imx8qm_ldb->clk_bypass)) {
+ ret = PTR_ERR(imx8qm_ldb->clk_bypass);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev,
+ "failed to get bypass clock: %d\n", ret);
+ return ret;
+ }
+
+ imx8qm_ldb->dev = dev;
+
+ ldb = &imx8qm_ldb->base;
+ ldb->dev = dev;
+ ldb->ctrl_reg = 0xe0;
+
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++)
+ ldb->channel[i] = &imx8qm_ldb->channel[i].base;
+
+ ret = ldb_init_helper(ldb);
+ if (ret)
+ return ret;
+
+ if (ldb->available_ch_cnt == 0) {
+ DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n");
+ return 0;
+ }
+
+ if (ldb->available_ch_cnt == 2) {
+ port1 = of_graph_get_port_by_id(ldb->channel[0]->np, 1);
+ port2 = of_graph_get_port_by_id(ldb->channel[1]->np, 1);
+ pixel_order =
+ drm_of_lvds_get_dual_link_pixel_order(port1, port2);
+ of_node_put(port1);
+ of_node_put(port2);
+
+ if (pixel_order != DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) {
+ DRM_DEV_ERROR(dev, "invalid dual link pixel order: %d\n",
+ pixel_order);
+ return -EINVAL;
+ }
+
+ imx8qm_ldb->active_chno = 0;
+ imx8qm_ldb_ch = &imx8qm_ldb->channel[0];
+ ldb_ch = &imx8qm_ldb_ch->base;
+ ldb_ch->link_type = pixel_order;
+ } else {
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
+ imx8qm_ldb_ch = &imx8qm_ldb->channel[i];
+ ldb_ch = &imx8qm_ldb_ch->base;
+
+ if (ldb_ch->is_available) {
+ imx8qm_ldb->active_chno = ldb_ch->chno;
+ break;
+ }
+ }
+ }
+
+ ret = imx8qm_ldb_get_phy(imx8qm_ldb);
+ if (ret)
+ return ret;
+
+ ret = ldb_find_next_bridge_helper(ldb);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, imx8qm_ldb);
+ pm_runtime_enable(dev);
+
+ ldb_add_bridge_helper(ldb, &imx8qm_ldb_bridge_funcs);
+
+ return ret;
+}
+
+static int imx8qm_ldb_remove(struct platform_device *pdev)
+{
+ struct imx8qm_ldb *imx8qm_ldb = platform_get_drvdata(pdev);
+ struct ldb *ldb = &imx8qm_ldb->base;
+
+ ldb_remove_bridge_helper(ldb);
+
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static int __maybe_unused imx8qm_ldb_runtime_suspend(struct device *dev)
+{
+ return 0;
+}
+
+static int __maybe_unused imx8qm_ldb_runtime_resume(struct device *dev)
+{
+ struct imx8qm_ldb *imx8qm_ldb = dev_get_drvdata(dev);
+ struct ldb *ldb = &imx8qm_ldb->base;
+
+ /* disable LDB by resetting the control register to POR default */
+ regmap_write(ldb->regmap, ldb->ctrl_reg, 0);
+
+ return 0;
+}
+
+static const struct dev_pm_ops imx8qm_ldb_pm_ops = {
+ SET_RUNTIME_PM_OPS(imx8qm_ldb_runtime_suspend,
+ imx8qm_ldb_runtime_resume, NULL)
+};
+
+static const struct of_device_id imx8qm_ldb_dt_ids[] = {
+ { .compatible = "fsl,imx8qm-ldb" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx8qm_ldb_dt_ids);
+
+static struct platform_driver imx8qm_ldb_driver = {
+ .probe = imx8qm_ldb_probe,
+ .remove = imx8qm_ldb_remove,
+ .driver = {
+ .pm = &imx8qm_ldb_pm_ops,
+ .name = DRIVER_NAME,
+ .of_match_table = imx8qm_ldb_dt_ids,
+ },
+};
+module_platform_driver(imx8qm_ldb_driver);
+
+MODULE_DESCRIPTION("i.MX8QM LVDS Display Bridge(LDB)/Pixel Mapper bridge driver");
+MODULE_AUTHOR("Liu Ying <[email protected]>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
--
2.7.4

2021-02-18 04:00:51

by Liu Ying

[permalink] [raw]
Subject: [PATCH v4 14/14] MAINTAINERS: add maintainer for DRM bridge drivers for i.MX SoCs

Add myself as the maintainer of DRM bridge drivers for i.MX SoCs.

Signed-off-by: Liu Ying <[email protected]>
---
v3->v4:
* No change.

v2->v3:
* No change.

v1->v2:
* No change.

MAINTAINERS | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 9d241b8..d96c917 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5892,6 +5892,16 @@ F: Documentation/devicetree/bindings/display/imx/
F: drivers/gpu/drm/imx/
F: drivers/gpu/ipu-v3/

+DRM DRIVERS FOR FREESCALE IMX BRIDGE
+M: Liu Ying <[email protected]>
+L: [email protected]
+S: Maintained
+F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
+F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
+F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
+F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
+F: drivers/gpu/drm/bridge/imx/
+
DRM DRIVERS FOR GMA500 (Poulsbo, Moorestown and derivative chipsets)
M: Patrik Jakobsson <[email protected]>
L: [email protected]
--
2.7.4

2021-02-18 04:01:17

by Liu Ying

[permalink] [raw]
Subject: [PATCH v4 09/14] drm/bridge: imx: Add i.MX8qxp pixel link to DPI support

This patch adds a drm bridge driver for i.MX8qxp pixel link to display
pixel interface(PXL2DPI). The PXL2DPI interfaces the pixel link 36-bit
data output and the DSI controller’s MIPI-DPI 24-bit data input, and
inputs of LVDS Display Bridge(LDB) module used in LVDS mode, to remap
the pixel color codings between those modules. The PXL2DPI is purely
combinatorial.

Signed-off-by: Liu Ying <[email protected]>
---
v3->v4:
* Use 'fsl,sc-resource' DT property to get the SCU resource ID associated with
the PXL2DPI instance instead of using alias ID. (Rob)

v2->v3:
* Call syscon_node_to_regmap() to get regmap instead of
syscon_regmap_lookup_by_phandle().

v1->v2:
* Drop unnecessary port availability check.

drivers/gpu/drm/bridge/imx/Kconfig | 8 +
drivers/gpu/drm/bridge/imx/Makefile | 1 +
drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c | 485 +++++++++++++++++++++++++++
3 files changed, 494 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c

diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
index 4d1f027..1ea1ce7 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -14,3 +14,11 @@ config DRM_IMX8QXP_PIXEL_LINK
help
Choose this to enable display pixel link found in
Freescale i.MX8qm/qxp processors.
+
+config DRM_IMX8QXP_PIXEL_LINK_TO_DPI
+ tristate "Freescale i.MX8QXP pixel link to display pixel interface"
+ depends on OF
+ select DRM_KMS_HELPER
+ help
+ Choose this to enable pixel link to display pixel interface(PXL2DPI)
+ found in Freescale i.MX8qxp processor.
diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
index c15469f..e74dd64 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
+obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
new file mode 100644
index 00000000..6696855
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
@@ -0,0 +1,485 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <linux/firmware/imx/svc/misc.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_of.h>
+#include <drm/drm_print.h>
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+#define PXL2DPI_CTRL 0x40
+#define CFG1_16BIT 0x0
+#define CFG2_16BIT 0x1
+#define CFG3_16BIT 0x2
+#define CFG1_18BIT 0x3
+#define CFG2_18BIT 0x4
+#define CFG_24BIT 0x5
+
+#define DRIVER_NAME "imx8qxp-pxl2dpi"
+
+struct imx8qxp_pxl2dpi {
+ struct regmap *regmap;
+ struct drm_bridge bridge;
+ struct drm_bridge *next_bridge;
+ struct drm_bridge *companion;
+ struct device *dev;
+ struct imx_sc_ipc *ipc_handle;
+ u32 sc_resource;
+ u32 in_bus_format;
+ u32 out_bus_format;
+ u32 pl_sel;
+};
+
+#define bridge_to_p2d(b) container_of(b, struct imx8qxp_pxl2dpi, bridge)
+
+static int imx8qxp_pxl2dpi_bridge_attach(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
+
+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+ DRM_DEV_ERROR(p2d->dev,
+ "do not support creating a drm_connector\n");
+ return -EINVAL;
+ }
+
+ if (!bridge->encoder) {
+ DRM_DEV_ERROR(p2d->dev, "missing encoder\n");
+ return -ENODEV;
+ }
+
+ return drm_bridge_attach(bridge->encoder,
+ p2d->next_bridge, bridge,
+ DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+}
+
+static int
+imx8qxp_pxl2dpi_bridge_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
+
+ p2d->in_bus_format = bridge_state->input_bus_cfg.format;
+ p2d->out_bus_format = bridge_state->output_bus_cfg.format;
+
+ return 0;
+}
+
+static void
+imx8qxp_pxl2dpi_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
+ struct imx8qxp_pxl2dpi *companion_p2d;
+ int ret;
+
+ ret = pm_runtime_get_sync(p2d->dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(p2d->dev,
+ "failed to get runtime PM sync: %d\n", ret);
+
+ ret = imx_sc_misc_set_control(p2d->ipc_handle, p2d->sc_resource,
+ IMX_SC_C_PXL_LINK_SEL, p2d->pl_sel);
+ if (ret)
+ DRM_DEV_ERROR(p2d->dev,
+ "failed to set pixel link selection(%u): %d\n",
+ p2d->pl_sel, ret);
+
+ switch (p2d->out_bus_format) {
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ regmap_write(p2d->regmap, PXL2DPI_CTRL, CFG_24BIT);
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
+ regmap_write(p2d->regmap, PXL2DPI_CTRL, CFG2_18BIT);
+ break;
+ default:
+ DRM_DEV_ERROR(p2d->dev,
+ "unsupported output bus format 0x%08x\n",
+ p2d->out_bus_format);
+ }
+
+ if (p2d->companion) {
+ companion_p2d = bridge_to_p2d(p2d->companion);
+
+ companion_p2d->in_bus_format = p2d->in_bus_format;
+ companion_p2d->out_bus_format = p2d->out_bus_format;
+
+ p2d->companion->funcs->mode_set(p2d->companion, mode,
+ adjusted_mode);
+ }
+}
+
+static void
+imx8qxp_pxl2dpi_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
+ int ret;
+
+ ret = pm_runtime_put(p2d->dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(p2d->dev, "failed to put runtime PM: %d\n", ret);
+
+ if (p2d->companion)
+ p2d->companion->funcs->atomic_disable(p2d->companion,
+ old_bridge_state);
+}
+
+static const u32 imx8qxp_pxl2dpi_bus_output_fmts[] = {
+ MEDIA_BUS_FMT_RGB888_1X24,
+ MEDIA_BUS_FMT_RGB666_1X24_CPADHI,
+};
+
+static bool imx8qxp_pxl2dpi_bus_output_fmt_supported(u32 fmt)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx8qxp_pxl2dpi_bus_output_fmts); i++) {
+ if (imx8qxp_pxl2dpi_bus_output_fmts[i] == fmt)
+ return true;
+ }
+
+ return false;
+}
+
+static u32 *
+imx8qxp_pxl2dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ u32 *input_fmts;
+
+ if (!imx8qxp_pxl2dpi_bus_output_fmt_supported(output_fmt))
+ return NULL;
+
+ *num_input_fmts = 1;
+
+ input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
+ if (!input_fmts)
+ return NULL;
+
+ switch (output_fmt) {
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X36_CPADLO;
+ break;
+ default:
+ kfree(input_fmts);
+ input_fmts = NULL;
+ break;
+ }
+
+ return input_fmts;
+}
+
+static u32 *
+imx8qxp_pxl2dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ unsigned int *num_output_fmts)
+{
+ *num_output_fmts = ARRAY_SIZE(imx8qxp_pxl2dpi_bus_output_fmts);
+ return kmemdup(imx8qxp_pxl2dpi_bus_output_fmts,
+ sizeof(imx8qxp_pxl2dpi_bus_output_fmts), GFP_KERNEL);
+}
+
+static const struct drm_bridge_funcs imx8qxp_pxl2dpi_bridge_funcs = {
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .attach = imx8qxp_pxl2dpi_bridge_attach,
+ .atomic_check = imx8qxp_pxl2dpi_bridge_atomic_check,
+ .mode_set = imx8qxp_pxl2dpi_bridge_mode_set,
+ .atomic_disable = imx8qxp_pxl2dpi_bridge_atomic_disable,
+ .atomic_get_input_bus_fmts =
+ imx8qxp_pxl2dpi_bridge_atomic_get_input_bus_fmts,
+ .atomic_get_output_bus_fmts =
+ imx8qxp_pxl2dpi_bridge_atomic_get_output_bus_fmts,
+};
+
+static struct device_node *
+imx8qxp_pxl2dpi_get_available_ep_from_port(struct imx8qxp_pxl2dpi *p2d,
+ u32 port_id)
+{
+ struct device_node *port, *ep;
+ int ep_cnt;
+
+ port = of_graph_get_port_by_id(p2d->dev->of_node, port_id);
+ if (!port) {
+ DRM_DEV_ERROR(p2d->dev, "failed to get port@%u\n", port_id);
+ return ERR_PTR(-ENODEV);
+ }
+
+ ep_cnt = of_get_available_child_count(port);
+ if (ep_cnt == 0) {
+ DRM_DEV_ERROR(p2d->dev, "no available endpoints of port@%u\n",
+ port_id);
+ ep = ERR_PTR(-ENODEV);
+ goto out;
+ } else if (ep_cnt > 1) {
+ DRM_DEV_ERROR(p2d->dev,
+ "invalid available endpoints of port@%u\n", port_id);
+ ep = ERR_PTR(-ENOTSUPP);
+ goto out;
+ }
+
+ ep = of_get_next_available_child(port, NULL);
+ if (!ep) {
+ DRM_DEV_ERROR(p2d->dev,
+ "failed to get available endpoint of port@%u\n",
+ port_id);
+ ep = ERR_PTR(-ENODEV);
+ goto out;
+ }
+out:
+ of_node_put(port);
+ return ep;
+}
+
+static struct drm_bridge *
+imx8qxp_pxl2dpi_find_next_bridge(struct imx8qxp_pxl2dpi *p2d)
+{
+ struct device_node *ep, *remote;
+ struct drm_bridge *next_bridge;
+ int ret;
+
+ ep = imx8qxp_pxl2dpi_get_available_ep_from_port(p2d, 1);
+ if (IS_ERR(ep)) {
+ ret = PTR_ERR(ep);
+ return ERR_PTR(ret);
+ }
+
+ remote = of_graph_get_remote_port_parent(ep);
+ if (!remote || !of_device_is_available(remote)) {
+ DRM_DEV_ERROR(p2d->dev, "no available remote\n");
+ next_bridge = ERR_PTR(-ENODEV);
+ goto out;
+ } else if (!of_device_is_available(remote->parent)) {
+ DRM_DEV_ERROR(p2d->dev, "remote parent is not available\n");
+ next_bridge = ERR_PTR(-ENODEV);
+ goto out;
+ }
+
+ next_bridge = of_drm_find_bridge(remote);
+ if (!next_bridge) {
+ next_bridge = ERR_PTR(-EPROBE_DEFER);
+ goto out;
+ }
+out:
+ of_node_put(remote);
+ of_node_put(ep);
+
+ return next_bridge;
+}
+
+static int imx8qxp_pxl2dpi_set_pixel_link_sel(struct imx8qxp_pxl2dpi *p2d)
+{
+ struct device_node *ep;
+ struct of_endpoint endpoint;
+ int ret;
+
+ ep = imx8qxp_pxl2dpi_get_available_ep_from_port(p2d, 0);
+ if (IS_ERR(ep))
+ return PTR_ERR(ep);
+
+ ret = of_graph_parse_endpoint(ep, &endpoint);
+ if (ret) {
+ DRM_DEV_ERROR(p2d->dev,
+ "failed to parse endpoint of port@0: %d\n", ret);
+ goto out;
+ }
+
+ p2d->pl_sel = endpoint.id;
+out:
+ of_node_put(ep);
+
+ return ret;
+}
+
+static int imx8qxp_pxl2dpi_parse_dt_companion(struct imx8qxp_pxl2dpi *p2d)
+{
+ struct imx8qxp_pxl2dpi *companion_p2d;
+ struct device *dev = p2d->dev;
+ struct device_node *companion;
+ struct device_node *port1, *port2;
+ const struct of_device_id *match;
+ int dual_link;
+ int ret = 0;
+
+ /* Locate the companion PXL2DPI for dual-link operation, if any. */
+ companion = of_parse_phandle(dev->of_node, "fsl,companion-pxl2dpi", 0);
+ if (!companion)
+ return 0;
+
+ if (!of_device_is_available(companion)) {
+ DRM_DEV_ERROR(dev, "companion PXL2DPI is not available\n");
+ ret = -ENODEV;
+ goto out;
+ }
+
+ /*
+ * Sanity check: the companion bridge must have the same compatible
+ * string.
+ */
+ match = of_match_device(dev->driver->of_match_table, dev);
+ if (!of_device_is_compatible(companion, match->compatible)) {
+ DRM_DEV_ERROR(dev, "companion PXL2DPI is incompatible\n");
+ ret = -ENXIO;
+ goto out;
+ }
+
+ p2d->companion = of_drm_find_bridge(companion);
+ if (!p2d->companion) {
+ ret = -EPROBE_DEFER;
+ DRM_DEV_DEBUG_DRIVER(p2d->dev,
+ "failed to find companion bridge: %d\n", ret);
+ goto out;
+ }
+
+ companion_p2d = bridge_to_p2d(p2d->companion);
+
+ /*
+ * We need to work out if the sink is expecting us to function in
+ * dual-link mode. We do this by looking at the DT port nodes that
+ * the next bridges are connected to. If they are marked as expecting
+ * even pixels and odd pixels than we need to use the companion PXL2DPI.
+ */
+ port1 = of_graph_get_port_by_id(p2d->next_bridge->of_node, 1);
+ port2 = of_graph_get_port_by_id(companion_p2d->next_bridge->of_node, 1);
+ dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2);
+ of_node_put(port1);
+ of_node_put(port2);
+
+ if (dual_link < 0) {
+ ret = dual_link;
+ DRM_DEV_ERROR(dev, "failed to get dual link pixel order: %d\n",
+ ret);
+ goto out;
+ }
+
+ DRM_DEV_DEBUG_DRIVER(dev,
+ "dual-link configuration detected (companion bridge %pOF)\n",
+ companion);
+out:
+ of_node_put(companion);
+ return ret;
+}
+
+static int imx8qxp_pxl2dpi_bridge_probe(struct platform_device *pdev)
+{
+ struct imx8qxp_pxl2dpi *p2d;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+ p2d = devm_kzalloc(dev, sizeof(*p2d), GFP_KERNEL);
+ if (!p2d)
+ return -ENOMEM;
+
+ p2d->regmap = syscon_node_to_regmap(np->parent);
+ if (IS_ERR(p2d->regmap)) {
+ ret = PTR_ERR(p2d->regmap);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ ret = imx_scu_get_handle(&p2d->ipc_handle);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n",
+ ret);
+ return ret;
+ }
+
+ p2d->dev = dev;
+
+ ret = of_property_read_u32(np, "fsl,sc-resource", &p2d->sc_resource);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to get SC resource %d\n", ret);
+ return ret;
+ }
+
+ p2d->next_bridge = imx8qxp_pxl2dpi_find_next_bridge(p2d);
+ if (IS_ERR(p2d->next_bridge)) {
+ ret = PTR_ERR(p2d->next_bridge);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = imx8qxp_pxl2dpi_set_pixel_link_sel(p2d);
+ if (ret)
+ return ret;
+
+ ret = imx8qxp_pxl2dpi_parse_dt_companion(p2d);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, p2d);
+ pm_runtime_enable(dev);
+
+ p2d->bridge.driver_private = p2d;
+ p2d->bridge.funcs = &imx8qxp_pxl2dpi_bridge_funcs;
+ p2d->bridge.of_node = np;
+
+ drm_bridge_add(&p2d->bridge);
+
+ return ret;
+}
+
+static int imx8qxp_pxl2dpi_bridge_remove(struct platform_device *pdev)
+{
+ struct imx8qxp_pxl2dpi *p2d = platform_get_drvdata(pdev);
+
+ drm_bridge_remove(&p2d->bridge);
+
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id imx8qxp_pxl2dpi_dt_ids[] = {
+ { .compatible = "fsl,imx8qxp-pxl2dpi", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx8qxp_pxl2dpi_dt_ids);
+
+static struct platform_driver imx8qxp_pxl2dpi_bridge_driver = {
+ .probe = imx8qxp_pxl2dpi_bridge_probe,
+ .remove = imx8qxp_pxl2dpi_bridge_remove,
+ .driver = {
+ .of_match_table = imx8qxp_pxl2dpi_dt_ids,
+ .name = DRIVER_NAME,
+ },
+};
+module_platform_driver(imx8qxp_pxl2dpi_bridge_driver);
+
+MODULE_DESCRIPTION("i.MX8QXP pixel link to DPI bridge driver");
+MODULE_AUTHOR("Liu Ying <[email protected]>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
--
2.7.4

2021-02-18 04:01:21

by Liu Ying

[permalink] [raw]
Subject: [PATCH v4 10/14] drm/bridge: imx: Add LDB driver helper support

This patch adds a helper to support LDB drm bridge drivers for
i.MX SoCs. Helper functions exported from this driver should
implement common logics for all LDB modules embedded in i.MX SoCs.

Signed-off-by: Liu Ying <[email protected]>
---
v3->v4:
* No change.

v2->v3:
* Call syscon_node_to_regmap() to get regmap instead of
syscon_regmap_lookup_by_phandle().

v1->v2:
* No change.

drivers/gpu/drm/bridge/imx/Kconfig | 8 +
drivers/gpu/drm/bridge/imx/Makefile | 1 +
drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 248 ++++++++++++++++++++++++++++
include/drm/bridge/imx_ldb_helper.h | 98 +++++++++++
4 files changed, 355 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
create mode 100644 include/drm/bridge/imx_ldb_helper.h

diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
index 1ea1ce7..23e24fd 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -1,3 +1,11 @@
+config DRM_IMX_LVDS_BRIDGE_HELPER
+ tristate "Freescale i.MX LVDS display bridge helper"
+ depends on OF
+ select DRM_PANEL_BRIDGE
+ help
+ Helper to support Freescale i.MX LVDS Display Bridge(LDB).
+ This bridge is embedded in a SoC.
+
config DRM_IMX8QXP_PIXEL_COMBINER
tristate "Freescale i.MX8QM/QXP pixel combiner"
depends on OF
diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
index e74dd64..902b703 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_DRM_IMX_LVDS_BRIDGE_HELPER) += imx-ldb-helper.o
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
diff --git a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
new file mode 100644
index 00000000..94d7f9e
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Sascha Hauer, Pengutronix
+ * Copyright 2019,2020 NXP
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+
+#include <drm/bridge/imx_ldb_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_print.h>
+
+bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch)
+{
+ return ldb_ch->link_type == LDB_CH_SINGLE_LINK;
+}
+EXPORT_SYMBOL_GPL(ldb_channel_is_single_link);
+
+bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch)
+{
+ return ldb_ch->link_type == LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS ||
+ ldb_ch->link_type == LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS;
+}
+EXPORT_SYMBOL_GPL(ldb_channel_is_split_link);
+
+int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+
+ ldb_ch->in_bus_format = bridge_state->input_bus_cfg.format;
+ ldb_ch->out_bus_format = bridge_state->output_bus_cfg.format;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ldb_bridge_atomic_check_helper);
+
+void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+
+ if (is_split)
+ ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
+
+ switch (ldb_ch->out_bus_format) {
+ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+ if (ldb_ch->chno == 0 || is_split)
+ ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
+ if (ldb_ch->chno == 1 || is_split)
+ ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+ if (ldb_ch->chno == 0 || is_split)
+ ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
+ LDB_BIT_MAP_CH0_JEIDA;
+ if (ldb_ch->chno == 1 || is_split)
+ ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
+ LDB_BIT_MAP_CH1_JEIDA;
+ break;
+ }
+}
+EXPORT_SYMBOL_GPL(ldb_bridge_mode_set_helper);
+
+void ldb_bridge_enable_helper(struct drm_bridge *bridge)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+
+ /*
+ * Platform specific bridge drivers should set ldb_ctrl properly
+ * for the enablement, so just write the ctrl_reg here.
+ */
+ regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
+}
+EXPORT_SYMBOL_GPL(ldb_bridge_enable_helper);
+
+void ldb_bridge_disable_helper(struct drm_bridge *bridge)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+
+ if (ldb_ch->chno == 0 || is_split)
+ ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
+ if (ldb_ch->chno == 1 || is_split)
+ ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
+
+ regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
+}
+EXPORT_SYMBOL_GPL(ldb_bridge_disable_helper);
+
+int ldb_bridge_attach_helper(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+
+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+ DRM_DEV_ERROR(ldb->dev,
+ "do not support creating a drm_connector\n");
+ return -EINVAL;
+ }
+
+ if (!bridge->encoder) {
+ DRM_DEV_ERROR(ldb->dev, "missing encoder\n");
+ return -ENODEV;
+ }
+
+ return drm_bridge_attach(bridge->encoder,
+ ldb_ch->next_bridge, bridge,
+ DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+}
+EXPORT_SYMBOL_GPL(ldb_bridge_attach_helper);
+
+int ldb_init_helper(struct ldb *ldb)
+{
+ struct device *dev = ldb->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *child;
+ int ret;
+ u32 i;
+
+ ldb->regmap = syscon_node_to_regmap(np->parent);
+ if (IS_ERR(ldb->regmap)) {
+ ret = PTR_ERR(ldb->regmap);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ for_each_available_child_of_node(np, child) {
+ struct ldb_channel *ldb_ch;
+
+ ret = of_property_read_u32(child, "reg", &i);
+ if (ret || i > MAX_LDB_CHAN_NUM - 1) {
+ ret = -EINVAL;
+ DRM_DEV_ERROR(dev,
+ "invalid channel node address: %u\n", i);
+ of_node_put(child);
+ return ret;
+ }
+
+ ldb_ch = ldb->channel[i];
+ ldb_ch->ldb = ldb;
+ ldb_ch->chno = i;
+ ldb_ch->is_available = true;
+ ldb_ch->np = child;
+
+ ldb->available_ch_cnt++;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ldb_init_helper);
+
+int ldb_find_next_bridge_helper(struct ldb *ldb)
+{
+ struct device *dev = ldb->dev;
+ struct ldb_channel *ldb_ch;
+ int ret, i;
+
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
+ ldb_ch = ldb->channel[i];
+
+ if (!ldb_ch->is_available)
+ continue;
+
+ ret = drm_of_find_panel_or_bridge(ldb_ch->np, 1, 0,
+ &ldb_ch->panel,
+ &ldb_ch->next_bridge);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev,
+ "failed to find panel or bridge: %d\n",
+ ret);
+ return ret;
+ }
+
+ if (ldb_ch->panel) {
+ ldb_ch->next_bridge = devm_drm_panel_bridge_add(dev,
+ ldb_ch->panel);
+ if (IS_ERR(ldb_ch->next_bridge)) {
+ ret = PTR_ERR(ldb_ch->next_bridge);
+ DRM_DEV_ERROR(dev,
+ "failed to add panel bridge: %d\n",
+ ret);
+ return ret;
+ }
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ldb_find_next_bridge_helper);
+
+void ldb_add_bridge_helper(struct ldb *ldb,
+ const struct drm_bridge_funcs *bridge_funcs)
+{
+ struct ldb_channel *ldb_ch;
+ int i;
+
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
+ ldb_ch = ldb->channel[i];
+
+ if (!ldb_ch->is_available)
+ continue;
+
+ ldb_ch->bridge.driver_private = ldb_ch;
+ ldb_ch->bridge.funcs = bridge_funcs;
+ ldb_ch->bridge.of_node = ldb_ch->np;
+
+ drm_bridge_add(&ldb_ch->bridge);
+ }
+}
+EXPORT_SYMBOL_GPL(ldb_add_bridge_helper);
+
+void ldb_remove_bridge_helper(struct ldb *ldb)
+{
+ struct ldb_channel *ldb_ch;
+ int i;
+
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
+ ldb_ch = ldb->channel[i];
+
+ if (!ldb_ch->is_available)
+ continue;
+
+ drm_bridge_remove(&ldb_ch->bridge);
+ }
+}
+EXPORT_SYMBOL_GPL(ldb_remove_bridge_helper);
+
+MODULE_DESCRIPTION("Freescale i.MX LVDS Display Bridge driver helper");
+MODULE_AUTHOR("Liu Ying <[email protected]>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:imx-ldb-helper");
diff --git a/include/drm/bridge/imx_ldb_helper.h b/include/drm/bridge/imx_ldb_helper.h
new file mode 100644
index 00000000..2a7ba97
--- /dev/null
+++ b/include/drm/bridge/imx_ldb_helper.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/*
+ * Copyright 2019,2020 NXP
+ */
+
+#ifndef __FSL_IMX_LDB__
+#define __FSL_IMX_LDB__
+
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_device.h>
+#include <drm/drm_encoder.h>
+#include <drm/drm_modeset_helper_vtables.h>
+#include <drm/drm_panel.h>
+
+#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
+#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
+#define LDB_CH0_MODE_EN_MASK (3 << 0)
+#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
+#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
+#define LDB_CH1_MODE_EN_MASK (3 << 2)
+#define LDB_SPLIT_MODE_EN (1 << 4)
+#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
+#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
+#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
+#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
+#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
+#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
+
+#define MAX_LDB_CHAN_NUM 2
+
+enum ldb_channel_link_type {
+ LDB_CH_SINGLE_LINK,
+ LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS,
+ LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS,
+};
+
+struct ldb;
+
+struct ldb_channel {
+ struct ldb *ldb;
+ struct drm_bridge bridge;
+ struct drm_panel *panel;
+ struct drm_bridge *next_bridge;
+ struct device_node *np;
+ u32 chno;
+ bool is_available;
+ u32 in_bus_format;
+ u32 out_bus_format;
+ enum ldb_channel_link_type link_type;
+};
+
+struct ldb {
+ struct regmap *regmap;
+ struct device *dev;
+ struct ldb_channel *channel[MAX_LDB_CHAN_NUM];
+ unsigned int ctrl_reg;
+ u32 ldb_ctrl;
+ unsigned int available_ch_cnt;
+};
+
+#define bridge_to_ldb_ch(b) container_of(b, struct ldb_channel, bridge)
+
+bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch);
+bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch);
+
+int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state);
+
+void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode);
+
+void ldb_bridge_enable_helper(struct drm_bridge *bridge);
+
+void ldb_bridge_disable_helper(struct drm_bridge *bridge);
+
+int ldb_bridge_attach_helper(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags);
+
+int ldb_init_helper(struct ldb *ldb);
+
+int ldb_find_next_bridge_helper(struct ldb *ldb);
+
+void ldb_add_bridge_helper(struct ldb *ldb,
+ const struct drm_bridge_funcs *bridge_funcs);
+
+void ldb_remove_bridge_helper(struct ldb *ldb);
+
+#endif /* __FSL_IMX_LDB__ */
--
2.7.4

2021-02-18 04:01:50

by Liu Ying

[permalink] [raw]
Subject: [PATCH v4 06/14] dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link binding

This patch adds bindings for i.MX8qm/qxp display pixel link.

Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
v3->v4:
* No change.

v2->v3:
* Add Rob's R-b tag.

v1->v2:
* Use graph schema. (Laurent)
* Require all four pixel link output ports. (Laurent)
* Mention pixel link is accessed via SCU firmware. (Rob)

.../display/bridge/fsl,imx8qxp-pixel-link.yaml | 106 +++++++++++++++++++++
1 file changed, 106 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
new file mode 100644
index 00000000..3af67cc
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Pixel Link
+
+maintainers:
+ - Liu Ying <[email protected]>
+
+description: |
+ The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
+ asynchronous linkage between pixel sources(display controller or
+ camera module) and pixel consumers(imaging or displays).
+ It consists of two distinct functions, a pixel transfer function and a
+ control interface. Multiple pixel channels can exist per one control channel.
+ This binding documentation is only for pixel links whose pixel sources are
+ display controllers.
+
+ The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
+ firmware.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qm-dc-pixel-link
+ - fsl,imx8qxp-dc-pixel-link
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The pixel link input port node from upstream video source.
+
+ patternProperties:
+ "^port@[1-4]$":
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The pixel link output port node to downstream bridge.
+
+ required:
+ - port@0
+ - port@1
+ - port@2
+ - port@3
+ - port@4
+
+required:
+ - compatible
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ dc0-pixel-link0 {
+ compatible = "fsl,imx8qxp-dc-pixel-link";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* from dc0 pixel combiner channel0 */
+ port@0 {
+ reg = <0>;
+
+ dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
+ remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
+ };
+ };
+
+ /* to PXL2DPIs in MIPI/LVDS combo subsystems */
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
+ };
+
+ dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
+ };
+ };
+
+ /* unused */
+ port@2 {
+ reg = <2>;
+ };
+
+ /* unused */
+ port@3 {
+ reg = <3>;
+ };
+
+ /* to imaging subsystem */
+ port@4 {
+ reg = <4>;
+ };
+ };
+ };
--
2.7.4

2021-02-18 04:02:12

by Liu Ying

[permalink] [raw]
Subject: [PATCH v4 11/14] dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge binding

This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).

Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
v3->v4:
* Add Rob's R-b tag.

v2->v3:
* Drop 'fsl,syscon' property. (Rob)
* Mention the CSR module controls LDB.

v1->v2:
* Use graph schema. (Laurent)
* Side note i.MX8qxp LDB official name 'pixel mapper'. (Laurent)

.../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 173 +++++++++++++++++++++
1 file changed, 173 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
new file mode 100644
index 00000000..9454300
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
@@ -0,0 +1,173 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp LVDS Display Bridge
+
+maintainers:
+ - Liu Ying <[email protected]>
+
+description: |
+ The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
+
+ The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
+ The CSR module, as a system controller, contains the LDB's configuration
+ registers.
+
+ For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
+ format and can map the input to VESA or JEIDA standards. The two channels
+ cannot be used simultaneously, that is to say, the user should pick one of
+ them to use. Two LDB channels from two LDB instances can work together in
+ LDB split mode to support a dual link LVDS display. The channel indexes
+ have to be different. Channel0 outputs odd pixels and channel1 outputs
+ even pixels.
+
+ For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
+ input color format. The two channels can be used simultaneously, either
+ in dual mode or split mode. In dual mode, the two channels output identical
+ data. In split mode, channel0 outputs odd pixels and channel1 outputs even
+ pixels.
+
+ A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
+ the SoC reference manuals. The pixel mapper uses logic of LDBs embedded in
+ i.MX6qdl/sx SoCs, i.e., it is essentially based on them. To keep the naming
+ consistency, this binding calls it LDB.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qm-ldb
+ - fsl,imx8qxp-ldb
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ clocks:
+ items:
+ - description: pixel clock
+ - description: bypass clock
+
+ clock-names:
+ items:
+ - const: pixel
+ - const: bypass
+
+ power-domains:
+ maxItems: 1
+
+ fsl,companion-ldb:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ A phandle which points to companion LDB which is used in LDB split mode.
+
+patternProperties:
+ "^channel@[0-1]$":
+ type: object
+ description: Represents a channel of LDB.
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ reg:
+ description: The channel index.
+ enum: [ 0, 1 ]
+
+ phys:
+ description: A phandle to the phy module representing the LVDS PHY.
+ maxItems: 1
+
+ phy-names:
+ const: lvds_phy
+
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Input port of the channel.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Output port of the channel.
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - reg
+ - phys
+ - phy-names
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - clocks
+ - clock-names
+ - power-domains
+ - channel@0
+ - channel@1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8qm-ldb
+ then:
+ properties:
+ fsl,companion-ldb: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ ldb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qxp-ldb";
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
+ clock-names = "pixel", "bypass";
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+
+ channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ phys = <&mipi_lvds_0_phy>;
+ phy-names = "lvds_phy";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
+ };
+ };
+ };
+
+ channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ phys = <&mipi_lvds_0_phy>;
+ phy-names = "lvds_phy";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
+ };
+ };
+ };
+ };
--
2.7.4

2021-02-18 04:02:20

by Liu Ying

[permalink] [raw]
Subject: [PATCH v4 08/14] dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding

This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).

Signed-off-by: Liu Ying <[email protected]>
---
v3->v4:
* Add 'fsl,sc-resource' property. (Rob)

v2->v3:
* Drop 'fsl,syscon' property. (Rob)
* Mention the CSR module controls PXL2DPI.

v1->v2:
* Use graph schema. (Laurent)

.../display/bridge/fsl,imx8qxp-pxl2dpi.yaml | 108 +++++++++++++++++++++
1 file changed, 108 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
new file mode 100644
index 00000000..e4e77fa
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
+
+maintainers:
+ - Liu Ying <[email protected]>
+
+description: |
+ The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
+ interfaces the pixel link 36-bit data output and the DSI controller’s
+ MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
+ used in LVDS mode, to remap the pixel color codings between those modules.
+ This module is purely combinatorial.
+
+ The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
+ The CSR module, as a system controller, contains the PXL2DPI's configuration
+ register.
+
+properties:
+ compatible:
+ const: fsl,imx8qxp-pxl2dpi
+
+ fsl,sc-resource:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The SCU resource ID associated with this PXL2DPI instance.
+
+ power-domains:
+ maxItems: 1
+
+ fsl,companion-pxl2dpi:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ A phandle which points to companion PXL2DPI which is used by downstream
+ LVDS Display Bridge(LDB) in split mode.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The PXL2DPI input port node from pixel link.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The PXL2DPI output port node to downstream bridge.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - fsl,sc-resource
+ - power-domains
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ pxl2dpi {
+ compatible = "fsl,imx8qxp-pxl2dpi";
+ fsl,sc-resource = <IMX_SC_R_MIPI_0>;
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>;
+ };
+
+ mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
+ };
+
+ mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
+ };
+ };
+ };
+ };
--
2.7.4

2021-02-18 04:02:47

by Liu Ying

[permalink] [raw]
Subject: [PATCH v4 07/14] drm/bridge: imx: Add i.MX8qm/qxp display pixel link support

This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link.
The pixel link forms a standard asynchronous linkage between
pixel sources(display controller or camera module) and pixel
consumers(imaging or displays). It consists of two distinct
functions, a pixel transfer function and a control interface.

Signed-off-by: Liu Ying <[email protected]>
---
v3->v4:
* No change.

v2->v3:
* Drop two macros which help define functions and define them directly.
* Properly disable all pixel link controls to POR value by calling
imx8qxp_pixel_link_disable_all_controls() from
imx8qxp_pixel_link_bridge_probe().

v1->v2:
* Rewrite the function to find the next bridge by properly using OF APIs
and dropping unnecessary DT validation. (Rob)

drivers/gpu/drm/bridge/imx/Kconfig | 8 +
drivers/gpu/drm/bridge/imx/Makefile | 1 +
drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 426 ++++++++++++++++++++++++
3 files changed, 435 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c

diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
index f1c91b6..4d1f027 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -6,3 +6,11 @@ config DRM_IMX8QXP_PIXEL_COMBINER
help
Choose this to enable pixel combiner found in
Freescale i.MX8qm/qxp processors.
+
+config DRM_IMX8QXP_PIXEL_LINK
+ tristate "Freescale i.MX8QM/QXP display pixel link"
+ depends on OF
+ select DRM_KMS_HELPER
+ help
+ Choose this to enable display pixel link found in
+ Freescale i.MX8qm/qxp processors.
diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
index 7d7c8d6..c15469f 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
+obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
new file mode 100644
index 00000000..2e5ba4a
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
@@ -0,0 +1,426 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <linux/firmware/imx/svc/misc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_graph.h>
+#include <linux/platform_device.h>
+
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_print.h>
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+#define DRIVER_NAME "imx8qxp-display-pixel-link"
+#define PL_MAX_MST_ADDR 3
+#define PL_MAX_NEXT_BRIDGES 2
+
+struct imx8qxp_pixel_link {
+ struct drm_bridge bridge;
+ struct drm_bridge *next_bridge;
+ struct device *dev;
+ struct imx_sc_ipc *ipc_handle;
+ int id;
+ int stream_id;
+ int dc_id;
+ u32 sink_rsc;
+ u32 mst_addr;
+ u8 mst_addr_ctrl;
+ u8 mst_en_ctrl;
+ u8 mst_vld_ctrl;
+ u8 sync_ctrl;
+};
+
+static void imx8qxp_pixel_link_enable_mst_en(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_en_ctrl, true);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to enable DC%d stream%d pixel link mst_en: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+}
+
+static void imx8qxp_pixel_link_enable_mst_vld(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_vld_ctrl, true);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to enable DC%d stream%d pixel link mst_vld: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+}
+
+static void imx8qxp_pixel_link_enable_sync(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->sync_ctrl, true);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to enable DC%d stream%d pixel link sync: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+}
+
+static int imx8qxp_pixel_link_disable_mst_en(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_en_ctrl, false);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to disable DC%d stream%d pixel link mst_en: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+
+ return ret;
+}
+
+static int imx8qxp_pixel_link_disable_mst_vld(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_vld_ctrl, false);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to disable DC%d stream%d pixel link mst_vld: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+
+ return ret;
+}
+
+static int imx8qxp_pixel_link_disable_sync(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->sync_ctrl, false);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to disable DC%d stream%d pixel link sync: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+
+ return ret;
+}
+
+static void imx8qxp_pixel_link_set_mst_addr(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle,
+ pl->sink_rsc, pl->mst_addr_ctrl,
+ pl->mst_addr);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to set DC%d stream%d pixel link mst addr(%u): %d\n",
+ pl->dc_id, pl->stream_id, pl->mst_addr, ret);
+}
+
+static int imx8qxp_pixel_link_bridge_attach(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ struct imx8qxp_pixel_link *pl = bridge->driver_private;
+
+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+ DRM_DEV_ERROR(pl->dev,
+ "do not support creating a drm_connector\n");
+ return -EINVAL;
+ }
+
+ if (!bridge->encoder) {
+ DRM_DEV_ERROR(pl->dev, "missing encoder\n");
+ return -ENODEV;
+ }
+
+ return drm_bridge_attach(bridge->encoder,
+ pl->next_bridge, bridge,
+ DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+}
+
+static void
+imx8qxp_pixel_link_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct imx8qxp_pixel_link *pl = bridge->driver_private;
+
+ imx8qxp_pixel_link_set_mst_addr(pl);
+}
+
+static void imx8qxp_pixel_link_bridge_atomic_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct imx8qxp_pixel_link *pl = bridge->driver_private;
+
+ imx8qxp_pixel_link_enable_mst_en(pl);
+ imx8qxp_pixel_link_enable_mst_vld(pl);
+ imx8qxp_pixel_link_enable_sync(pl);
+}
+
+static void imx8qxp_pixel_link_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct imx8qxp_pixel_link *pl = bridge->driver_private;
+
+ imx8qxp_pixel_link_disable_mst_en(pl);
+ imx8qxp_pixel_link_disable_mst_vld(pl);
+ imx8qxp_pixel_link_disable_sync(pl);
+}
+
+static const u32 imx8qxp_pixel_link_bus_output_fmts[] = {
+ MEDIA_BUS_FMT_RGB888_1X36_CPADLO,
+ MEDIA_BUS_FMT_RGB666_1X36_CPADLO,
+};
+
+static bool imx8qxp_pixel_link_bus_output_fmt_supported(u32 fmt)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts); i++) {
+ if (imx8qxp_pixel_link_bus_output_fmts[i] == fmt)
+ return true;
+ }
+
+ return false;
+}
+
+static u32 *
+imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ u32 *input_fmts;
+
+ if (!imx8qxp_pixel_link_bus_output_fmt_supported(output_fmt))
+ return NULL;
+
+ *num_input_fmts = 1;
+
+ input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
+ if (!input_fmts)
+ return NULL;
+
+ input_fmts[0] = output_fmt;
+
+ return input_fmts;
+}
+
+static u32 *
+imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ unsigned int *num_output_fmts)
+{
+ *num_output_fmts = ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts);
+ return kmemdup(imx8qxp_pixel_link_bus_output_fmts,
+ sizeof(imx8qxp_pixel_link_bus_output_fmts), GFP_KERNEL);
+}
+
+static const struct drm_bridge_funcs imx8qxp_pixel_link_bridge_funcs = {
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .attach = imx8qxp_pixel_link_bridge_attach,
+ .mode_set = imx8qxp_pixel_link_bridge_mode_set,
+ .atomic_enable = imx8qxp_pixel_link_bridge_atomic_enable,
+ .atomic_disable = imx8qxp_pixel_link_bridge_atomic_disable,
+ .atomic_get_input_bus_fmts =
+ imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts,
+ .atomic_get_output_bus_fmts =
+ imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts,
+};
+
+static int imx8qxp_pixel_link_disable_all_controls(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx8qxp_pixel_link_disable_mst_en(pl);
+ if (ret)
+ return ret;
+
+ ret = imx8qxp_pixel_link_disable_mst_vld(pl);
+ if (ret)
+ return ret;
+
+ return imx8qxp_pixel_link_disable_sync(pl);
+}
+
+static struct drm_bridge *
+imx8qxp_pixel_link_find_next_bridge(struct imx8qxp_pixel_link *pl)
+{
+ struct device_node *np = pl->dev->of_node;
+ struct device_node *port, *remote;
+ struct drm_bridge *next_bridge[PL_MAX_NEXT_BRIDGES];
+ u32 port_id;
+ bool found_port = false;
+ int reg, ep_cnt = 0;
+ int bridge_sel = 0; /* select the first next bridge by default */
+
+ for (port_id = 1; port_id <= PL_MAX_MST_ADDR + 1; port_id++) {
+ port = of_graph_get_port_by_id(np, port_id);
+ if (!port)
+ continue;
+
+ if (of_device_is_available(port)) {
+ found_port = true;
+ of_node_put(port);
+ break;
+ }
+
+ of_node_put(port);
+ }
+
+ if (!found_port) {
+ DRM_DEV_ERROR(pl->dev, "no available output port\n");
+ return ERR_PTR(-ENODEV);
+ }
+
+ for (reg = 0; reg < PL_MAX_NEXT_BRIDGES; reg++) {
+ remote = of_graph_get_remote_node(np, port_id, reg);
+ if (!remote)
+ continue;
+
+ if (!of_device_is_available(remote->parent)) {
+ DRM_DEV_DEBUG(pl->dev,
+ "port%u endpoint%u remote parent is not available\n",
+ port_id, reg);
+ of_node_put(remote);
+ continue;
+ }
+
+ next_bridge[ep_cnt] = of_drm_find_bridge(remote);
+ if (!next_bridge[ep_cnt]) {
+ of_node_put(remote);
+ return ERR_PTR(-EPROBE_DEFER);
+ }
+
+ /* specially select the next bridge with companion PXL2DPI */
+ if (of_find_property(remote, "fsl,companion-pxl2dpi", NULL))
+ bridge_sel = ep_cnt;
+
+ ep_cnt++;
+
+ of_node_put(remote);
+ }
+
+ pl->mst_addr = port_id - 1;
+
+ return next_bridge[bridge_sel];
+}
+
+static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev)
+{
+ struct imx8qxp_pixel_link *pl;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+ pl = devm_kzalloc(dev, sizeof(*pl), GFP_KERNEL);
+ if (!pl)
+ return -ENOMEM;
+
+ ret = imx_scu_get_handle(&pl->ipc_handle);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n",
+ ret);
+ return ret;
+ }
+
+ pl->id = of_alias_get_id(np, "dc_pl");
+ if (pl->id < 0) {
+ DRM_DEV_ERROR(dev,
+ "failed to get pixel link node alias id: %d\n",
+ pl->id);
+ return pl->id;
+ }
+
+ pl->dev = dev;
+
+ pl->dc_id = pl->id / 2;
+ pl->stream_id = pl->id % 2;
+
+ pl->sink_rsc = pl->dc_id ? IMX_SC_R_DC_1 : IMX_SC_R_DC_0;
+
+ if (pl->stream_id == 0) {
+ pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST1_ADDR;
+ pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST1_ENB;
+ pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST1_VLD;
+ pl->sync_ctrl = IMX_SC_C_SYNC_CTRL0;
+ } else {
+ pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST2_ADDR;
+ pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST2_ENB;
+ pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST2_VLD;
+ pl->sync_ctrl = IMX_SC_C_SYNC_CTRL1;
+ }
+
+ /* disable all controls to POR default */
+ ret = imx8qxp_pixel_link_disable_all_controls(pl);
+ if (ret)
+ return ret;
+
+ pl->next_bridge = imx8qxp_pixel_link_find_next_bridge(pl);
+ if (IS_ERR(pl->next_bridge)) {
+ ret = PTR_ERR(pl->next_bridge);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n",
+ ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, pl);
+
+ pl->bridge.driver_private = pl;
+ pl->bridge.funcs = &imx8qxp_pixel_link_bridge_funcs;
+ pl->bridge.of_node = np;
+
+ drm_bridge_add(&pl->bridge);
+
+ return ret;
+}
+
+static int imx8qxp_pixel_link_bridge_remove(struct platform_device *pdev)
+{
+ struct imx8qxp_pixel_link *pl = platform_get_drvdata(pdev);
+
+ drm_bridge_remove(&pl->bridge);
+
+ return 0;
+}
+
+static const struct of_device_id imx8qxp_pixel_link_dt_ids[] = {
+ { .compatible = "fsl,imx8qm-dc-pixel-link", },
+ { .compatible = "fsl,imx8qxp-dc-pixel-link", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx8qxp_pixel_link_dt_ids);
+
+static struct platform_driver imx8qxp_pixel_link_bridge_driver = {
+ .probe = imx8qxp_pixel_link_bridge_probe,
+ .remove = imx8qxp_pixel_link_bridge_remove,
+ .driver = {
+ .of_match_table = imx8qxp_pixel_link_dt_ids,
+ .name = DRIVER_NAME,
+ },
+};
+module_platform_driver(imx8qxp_pixel_link_bridge_driver);
+
+MODULE_DESCRIPTION("i.MX8QXP/QM display pixel link bridge driver");
+MODULE_AUTHOR("Liu Ying <[email protected]>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
--
2.7.4

2021-02-26 12:02:23

by Robert Foss

[permalink] [raw]
Subject: Re: [PATCH v4 02/14] media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner

Hey Liu,

This patch looks good to me
Reviewed-by: Robert Foss <[email protected]>

On Thu, 18 Feb 2021 at 04:56, Liu Ying <[email protected]> wrote:
>
> This patch adds RGB666_1X30_CPADLO, RGB888_1X30_CPADLO, RGB666_1X36_CPADLO
> and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp pixel combiner.
> The RGB pixels with padding low per component are transmitted on a 30-bit
> input bus(10-bit per component) from a display controller or a 36-bit
> output bus(12-bit per component) to a pixel link.
>
> Signed-off-by: Liu Ying <[email protected]>
> ---
> v3->v4:
> * No change.
>
> v2->v3:
> * No change.
>
> v1->v2:
> * No change.
>
> include/uapi/linux/media-bus-format.h | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h
> index 0dfc11e..ec3323d 100644
> --- a/include/uapi/linux/media-bus-format.h
> +++ b/include/uapi/linux/media-bus-format.h
> @@ -34,7 +34,7 @@
>
> #define MEDIA_BUS_FMT_FIXED 0x0001
>
> -/* RGB - next is 0x101e */
> +/* RGB - next is 0x1022 */
> #define MEDIA_BUS_FMT_RGB444_1X12 0x1016
> #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
> #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
> @@ -59,9 +59,13 @@
> #define MEDIA_BUS_FMT_RGB888_3X8_DELTA 0x101d
> #define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011
> #define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012
> +#define MEDIA_BUS_FMT_RGB666_1X30_CPADLO 0x101e
> +#define MEDIA_BUS_FMT_RGB888_1X30_CPADLO 0x101f
> #define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d
> #define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f
> #define MEDIA_BUS_FMT_RGB101010_1X30 0x1018
> +#define MEDIA_BUS_FMT_RGB666_1X36_CPADLO 0x1020
> +#define MEDIA_BUS_FMT_RGB888_1X36_CPADLO 0x1021
> #define MEDIA_BUS_FMT_RGB121212_1X36 0x1019
> #define MEDIA_BUS_FMT_RGB161616_1X48 0x101a
>
> --
> 2.7.4
>

2021-03-04 06:29:49

by Robert Foss

[permalink] [raw]
Subject: Re: [PATCH v4 10/14] drm/bridge: imx: Add LDB driver helper support

Hey Liu,

Thanks for submitting this patch.

On Thu, 18 Feb 2021 at 04:59, Liu Ying <[email protected]> wrote:
>
> This patch adds a helper to support LDB drm bridge drivers for
> i.MX SoCs. Helper functions exported from this driver should
> implement common logics for all LDB modules embedded in i.MX SoCs.
>
> Signed-off-by: Liu Ying <[email protected]>
> ---
> v3->v4:
> * No change.
>
> v2->v3:
> * Call syscon_node_to_regmap() to get regmap instead of
> syscon_regmap_lookup_by_phandle().
>
> v1->v2:
> * No change.
>
> drivers/gpu/drm/bridge/imx/Kconfig | 8 +
> drivers/gpu/drm/bridge/imx/Makefile | 1 +
> drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 248 ++++++++++++++++++++++++++++
> include/drm/bridge/imx_ldb_helper.h | 98 +++++++++++
> 4 files changed, 355 insertions(+)
> create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
> create mode 100644 include/drm/bridge/imx_ldb_helper.h
>
> diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
> index 1ea1ce7..23e24fd 100644
> --- a/drivers/gpu/drm/bridge/imx/Kconfig
> +++ b/drivers/gpu/drm/bridge/imx/Kconfig
> @@ -1,3 +1,11 @@
> +config DRM_IMX_LVDS_BRIDGE_HELPER
> + tristate "Freescale i.MX LVDS display bridge helper"
> + depends on OF
> + select DRM_PANEL_BRIDGE
> + help
> + Helper to support Freescale i.MX LVDS Display Bridge(LDB).
> + This bridge is embedded in a SoC.
> +
> config DRM_IMX8QXP_PIXEL_COMBINER
> tristate "Freescale i.MX8QM/QXP pixel combiner"
> depends on OF
> diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
> index e74dd64..902b703 100644
> --- a/drivers/gpu/drm/bridge/imx/Makefile
> +++ b/drivers/gpu/drm/bridge/imx/Makefile
> @@ -1,3 +1,4 @@
> +obj-$(CONFIG_DRM_IMX_LVDS_BRIDGE_HELPER) += imx-ldb-helper.o
> obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
> obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
> obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
> diff --git a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
> new file mode 100644
> index 00000000..94d7f9e
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
> @@ -0,0 +1,248 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2012 Sascha Hauer, Pengutronix
> + * Copyright 2019,2020 NXP
> + */
> +
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/regmap.h>
> +
> +#include <drm/bridge/imx_ldb_helper.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_print.h>
> +
> +bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch)
> +{
> + return ldb_ch->link_type == LDB_CH_SINGLE_LINK;
> +}
> +EXPORT_SYMBOL_GPL(ldb_channel_is_single_link);
> +
> +bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch)
> +{
> + return ldb_ch->link_type == LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS ||
> + ldb_ch->link_type == LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS;
> +}
> +EXPORT_SYMBOL_GPL(ldb_channel_is_split_link);
> +
> +int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
> + struct drm_bridge_state *bridge_state,
> + struct drm_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state)
> +{
> + struct ldb_channel *ldb_ch = bridge->driver_private;
> +
> + ldb_ch->in_bus_format = bridge_state->input_bus_cfg.format;
> + ldb_ch->out_bus_format = bridge_state->output_bus_cfg.format;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(ldb_bridge_atomic_check_helper);
> +
> +void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
> + const struct drm_display_mode *mode,
> + const struct drm_display_mode *adjusted_mode)
> +{
> + struct ldb_channel *ldb_ch = bridge->driver_private;
> + struct ldb *ldb = ldb_ch->ldb;
> + bool is_split = ldb_channel_is_split_link(ldb_ch);
> +
> + if (is_split)
> + ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
> +
> + switch (ldb_ch->out_bus_format) {
> + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
> + break;
> + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
> + if (ldb_ch->chno == 0 || is_split)
> + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
> + if (ldb_ch->chno == 1 || is_split)
> + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
> + break;
> + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
> + if (ldb_ch->chno == 0 || is_split)
> + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
> + LDB_BIT_MAP_CH0_JEIDA;
> + if (ldb_ch->chno == 1 || is_split)
> + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
> + LDB_BIT_MAP_CH1_JEIDA;
> + break;
> + }
> +}
> +EXPORT_SYMBOL_GPL(ldb_bridge_mode_set_helper);
> +
> +void ldb_bridge_enable_helper(struct drm_bridge *bridge)
> +{
> + struct ldb_channel *ldb_ch = bridge->driver_private;
> + struct ldb *ldb = ldb_ch->ldb;
> +
> + /*
> + * Platform specific bridge drivers should set ldb_ctrl properly
> + * for the enablement, so just write the ctrl_reg here.
> + */
> + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
> +}
> +EXPORT_SYMBOL_GPL(ldb_bridge_enable_helper);
> +
> +void ldb_bridge_disable_helper(struct drm_bridge *bridge)
> +{
> + struct ldb_channel *ldb_ch = bridge->driver_private;
> + struct ldb *ldb = ldb_ch->ldb;
> + bool is_split = ldb_channel_is_split_link(ldb_ch);
> +
> + if (ldb_ch->chno == 0 || is_split)
> + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
> + if (ldb_ch->chno == 1 || is_split)
> + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
> +
> + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
> +}
> +EXPORT_SYMBOL_GPL(ldb_bridge_disable_helper);
> +
> +int ldb_bridge_attach_helper(struct drm_bridge *bridge,
> + enum drm_bridge_attach_flags flags)
> +{
> + struct ldb_channel *ldb_ch = bridge->driver_private;
> + struct ldb *ldb = ldb_ch->ldb;
> +
> + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
> + DRM_DEV_ERROR(ldb->dev,
> + "do not support creating a drm_connector\n");
> + return -EINVAL;
> + }
> +
> + if (!bridge->encoder) {
> + DRM_DEV_ERROR(ldb->dev, "missing encoder\n");
> + return -ENODEV;
> + }
> +
> + return drm_bridge_attach(bridge->encoder,
> + ldb_ch->next_bridge, bridge,
> + DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> +}
> +EXPORT_SYMBOL_GPL(ldb_bridge_attach_helper);
> +
> +int ldb_init_helper(struct ldb *ldb)
> +{
> + struct device *dev = ldb->dev;
> + struct device_node *np = dev->of_node;
> + struct device_node *child;
> + int ret;
> + u32 i;
> +
> + ldb->regmap = syscon_node_to_regmap(np->parent);
> + if (IS_ERR(ldb->regmap)) {
> + ret = PTR_ERR(ldb->regmap);
> + if (ret != -EPROBE_DEFER)
> + DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret);
> + return ret;
> + }
> +
> + for_each_available_child_of_node(np, child) {
> + struct ldb_channel *ldb_ch;
> +
> + ret = of_property_read_u32(child, "reg", &i);
> + if (ret || i > MAX_LDB_CHAN_NUM - 1) {
> + ret = -EINVAL;
> + DRM_DEV_ERROR(dev,
> + "invalid channel node address: %u\n", i);
> + of_node_put(child);
> + return ret;
> + }
> +
> + ldb_ch = ldb->channel[i];
> + ldb_ch->ldb = ldb;
> + ldb_ch->chno = i;
> + ldb_ch->is_available = true;
> + ldb_ch->np = child;
> +
> + ldb->available_ch_cnt++;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(ldb_init_helper);
> +
> +int ldb_find_next_bridge_helper(struct ldb *ldb)
> +{
> + struct device *dev = ldb->dev;
> + struct ldb_channel *ldb_ch;
> + int ret, i;
> +
> + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
> + ldb_ch = ldb->channel[i];
> +
> + if (!ldb_ch->is_available)
> + continue;
> +
> + ret = drm_of_find_panel_or_bridge(ldb_ch->np, 1, 0,
> + &ldb_ch->panel,
> + &ldb_ch->next_bridge);
> + if (ret) {
> + if (ret != -EPROBE_DEFER)
> + DRM_DEV_ERROR(dev,
> + "failed to find panel or bridge: %d\n",
> + ret);
> + return ret;
> + }
> +
> + if (ldb_ch->panel) {
> + ldb_ch->next_bridge = devm_drm_panel_bridge_add(dev,
> + ldb_ch->panel);
> + if (IS_ERR(ldb_ch->next_bridge)) {
> + ret = PTR_ERR(ldb_ch->next_bridge);
> + DRM_DEV_ERROR(dev,
> + "failed to add panel bridge: %d\n",
> + ret);
> + return ret;
> + }
> + }
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(ldb_find_next_bridge_helper);
> +
> +void ldb_add_bridge_helper(struct ldb *ldb,
> + const struct drm_bridge_funcs *bridge_funcs)
> +{
> + struct ldb_channel *ldb_ch;
> + int i;
> +
> + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
> + ldb_ch = ldb->channel[i];
> +
> + if (!ldb_ch->is_available)
> + continue;
> +
> + ldb_ch->bridge.driver_private = ldb_ch;
> + ldb_ch->bridge.funcs = bridge_funcs;
> + ldb_ch->bridge.of_node = ldb_ch->np;
> +
> + drm_bridge_add(&ldb_ch->bridge);
> + }
> +}
> +EXPORT_SYMBOL_GPL(ldb_add_bridge_helper);
> +
> +void ldb_remove_bridge_helper(struct ldb *ldb)
> +{
> + struct ldb_channel *ldb_ch;
> + int i;
> +
> + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
> + ldb_ch = ldb->channel[i];
> +
> + if (!ldb_ch->is_available)
> + continue;
> +
> + drm_bridge_remove(&ldb_ch->bridge);
> + }
> +}
> +EXPORT_SYMBOL_GPL(ldb_remove_bridge_helper);
> +
> +MODULE_DESCRIPTION("Freescale i.MX LVDS Display Bridge driver helper");
> +MODULE_AUTHOR("Liu Ying <[email protected]>");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:imx-ldb-helper");

I'm not entirely sure why this set of helper functions should be a
module. It's not a driver, but rather a toolbox for the LDB driver,
which is fine, but there is no situation I can see where this module
would be unloaded and the LDB driver would be loaded.

> diff --git a/include/drm/bridge/imx_ldb_helper.h b/include/drm/bridge/imx_ldb_helper.h
> new file mode 100644
> index 00000000..2a7ba97
> --- /dev/null
> +++ b/include/drm/bridge/imx_ldb_helper.h

This header is specific to this driver, and I would expect it to not
be useful to other drivers. Additionally the filename has a different
format than the .c file it corresponds to. I would change the name and
path to "drivers/gpu/drm/bridge/imx/imx-ldb-helper.h".

> @@ -0,0 +1,98 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +
> +/*
> + * Copyright 2019,2020 NXP
> + */
> +
> +#ifndef __FSL_IMX_LDB__
> +#define __FSL_IMX_LDB__
> +
> +#include <linux/device.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/regmap.h>
> +
> +#include <drm/drm_atomic.h>
> +#include <drm/drm_bridge.h>
> +#include <drm/drm_device.h>
> +#include <drm/drm_encoder.h>
> +#include <drm/drm_modeset_helper_vtables.h>
> +#include <drm/drm_panel.h>
> +
> +#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
> +#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
> +#define LDB_CH0_MODE_EN_MASK (3 << 0)
> +#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
> +#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
> +#define LDB_CH1_MODE_EN_MASK (3 << 2)
> +#define LDB_SPLIT_MODE_EN (1 << 4)
> +#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
> +#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
> +#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
> +#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
> +#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
> +#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
> +
> +#define MAX_LDB_CHAN_NUM 2
> +
> +enum ldb_channel_link_type {
> + LDB_CH_SINGLE_LINK,
> + LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS,
> + LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS,
> +};
> +
> +struct ldb;
> +
> +struct ldb_channel {
> + struct ldb *ldb;
> + struct drm_bridge bridge;
> + struct drm_panel *panel;
> + struct drm_bridge *next_bridge;
> + struct device_node *np;
> + u32 chno;
> + bool is_available;
> + u32 in_bus_format;
> + u32 out_bus_format;
> + enum ldb_channel_link_type link_type;
> +};
> +
> +struct ldb {
> + struct regmap *regmap;
> + struct device *dev;
> + struct ldb_channel *channel[MAX_LDB_CHAN_NUM];
> + unsigned int ctrl_reg;
> + u32 ldb_ctrl;
> + unsigned int available_ch_cnt;
> +};
> +
> +#define bridge_to_ldb_ch(b) container_of(b, struct ldb_channel, bridge)
> +
> +bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch);
> +bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch);
> +
> +int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
> + struct drm_bridge_state *bridge_state,
> + struct drm_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state);
> +
> +void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
> + const struct drm_display_mode *mode,
> + const struct drm_display_mode *adjusted_mode);
> +
> +void ldb_bridge_enable_helper(struct drm_bridge *bridge);
> +
> +void ldb_bridge_disable_helper(struct drm_bridge *bridge);
> +
> +int ldb_bridge_attach_helper(struct drm_bridge *bridge,
> + enum drm_bridge_attach_flags flags);
> +
> +int ldb_init_helper(struct ldb *ldb);
> +
> +int ldb_find_next_bridge_helper(struct ldb *ldb);
> +
> +void ldb_add_bridge_helper(struct ldb *ldb,
> + const struct drm_bridge_funcs *bridge_funcs);
> +
> +void ldb_remove_bridge_helper(struct ldb *ldb);
> +
> +#endif /* __FSL_IMX_LDB__ */
> --
> 2.7.4
>

2021-03-04 06:30:26

by Robert Foss

[permalink] [raw]
Subject: Re: [PATCH v4 07/14] drm/bridge: imx: Add i.MX8qm/qxp display pixel link support

Hey Liu,

Thanks for submitting this patch.

I only have one comment below. With that addressed, feel free to add my r-b.

Reviewed-by: Robert Foss <[email protected]>

On Thu, 18 Feb 2021 at 04:59, Liu Ying <[email protected]> wrote:
>
> This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link.
> The pixel link forms a standard asynchronous linkage between
> pixel sources(display controller or camera module) and pixel
> consumers(imaging or displays). It consists of two distinct
> functions, a pixel transfer function and a control interface.
>
> Signed-off-by: Liu Ying <[email protected]>
> ---
> v3->v4:
> * No change.
>
> v2->v3:
> * Drop two macros which help define functions and define them directly.
> * Properly disable all pixel link controls to POR value by calling
> imx8qxp_pixel_link_disable_all_controls() from
> imx8qxp_pixel_link_bridge_probe().
>
> v1->v2:
> * Rewrite the function to find the next bridge by properly using OF APIs
> and dropping unnecessary DT validation. (Rob)
>
> drivers/gpu/drm/bridge/imx/Kconfig | 8 +
> drivers/gpu/drm/bridge/imx/Makefile | 1 +
> drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 426 ++++++++++++++++++++++++
> 3 files changed, 435 insertions(+)
> create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
>
> diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
> index f1c91b6..4d1f027 100644
> --- a/drivers/gpu/drm/bridge/imx/Kconfig
> +++ b/drivers/gpu/drm/bridge/imx/Kconfig
> @@ -6,3 +6,11 @@ config DRM_IMX8QXP_PIXEL_COMBINER
> help
> Choose this to enable pixel combiner found in
> Freescale i.MX8qm/qxp processors.
> +
> +config DRM_IMX8QXP_PIXEL_LINK
> + tristate "Freescale i.MX8QM/QXP display pixel link"
> + depends on OF
> + select DRM_KMS_HELPER
> + help
> + Choose this to enable display pixel link found in
> + Freescale i.MX8qm/qxp processors.
> diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
> index 7d7c8d6..c15469f 100644
> --- a/drivers/gpu/drm/bridge/imx/Makefile
> +++ b/drivers/gpu/drm/bridge/imx/Makefile
> @@ -1 +1,2 @@
> obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
> +obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
> diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
> new file mode 100644
> index 00000000..2e5ba4a
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
> @@ -0,0 +1,426 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +/*
> + * Copyright 2020 NXP
> + */
> +
> +#include <linux/firmware/imx/svc/misc.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_graph.h>
> +#include <linux/platform_device.h>
> +
> +#include <drm/drm_atomic_state_helper.h>
> +#include <drm/drm_bridge.h>
> +#include <drm/drm_print.h>
> +
> +#include <dt-bindings/firmware/imx/rsrc.h>
> +
> +#define DRIVER_NAME "imx8qxp-display-pixel-link"
> +#define PL_MAX_MST_ADDR 3
> +#define PL_MAX_NEXT_BRIDGES 2
> +
> +struct imx8qxp_pixel_link {
> + struct drm_bridge bridge;
> + struct drm_bridge *next_bridge;
> + struct device *dev;
> + struct imx_sc_ipc *ipc_handle;
> + int id;
> + int stream_id;
> + int dc_id;
> + u32 sink_rsc;
> + u32 mst_addr;
> + u8 mst_addr_ctrl;
> + u8 mst_en_ctrl;
> + u8 mst_vld_ctrl;
> + u8 sync_ctrl;
> +};
> +
> +static void imx8qxp_pixel_link_enable_mst_en(struct imx8qxp_pixel_link *pl)
> +{
> + int ret;
> +
> + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
> + pl->mst_en_ctrl, true);
> + if (ret)
> + DRM_DEV_ERROR(pl->dev,
> + "failed to enable DC%d stream%d pixel link mst_en: %d\n",
> + pl->dc_id, pl->stream_id, ret);
> +}
> +
> +static void imx8qxp_pixel_link_enable_mst_vld(struct imx8qxp_pixel_link *pl)
> +{
> + int ret;
> +
> + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
> + pl->mst_vld_ctrl, true);
> + if (ret)
> + DRM_DEV_ERROR(pl->dev,
> + "failed to enable DC%d stream%d pixel link mst_vld: %d\n",
> + pl->dc_id, pl->stream_id, ret);
> +}
> +
> +static void imx8qxp_pixel_link_enable_sync(struct imx8qxp_pixel_link *pl)
> +{
> + int ret;
> +
> + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
> + pl->sync_ctrl, true);
> + if (ret)
> + DRM_DEV_ERROR(pl->dev,
> + "failed to enable DC%d stream%d pixel link sync: %d\n",
> + pl->dc_id, pl->stream_id, ret);
> +}
> +
> +static int imx8qxp_pixel_link_disable_mst_en(struct imx8qxp_pixel_link *pl)
> +{
> + int ret;
> +
> + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
> + pl->mst_en_ctrl, false);
> + if (ret)
> + DRM_DEV_ERROR(pl->dev,
> + "failed to disable DC%d stream%d pixel link mst_en: %d\n",
> + pl->dc_id, pl->stream_id, ret);
> +
> + return ret;
> +}
> +
> +static int imx8qxp_pixel_link_disable_mst_vld(struct imx8qxp_pixel_link *pl)
> +{
> + int ret;
> +
> + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
> + pl->mst_vld_ctrl, false);
> + if (ret)
> + DRM_DEV_ERROR(pl->dev,
> + "failed to disable DC%d stream%d pixel link mst_vld: %d\n",
> + pl->dc_id, pl->stream_id, ret);
> +
> + return ret;
> +}
> +
> +static int imx8qxp_pixel_link_disable_sync(struct imx8qxp_pixel_link *pl)
> +{
> + int ret;
> +
> + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
> + pl->sync_ctrl, false);
> + if (ret)
> + DRM_DEV_ERROR(pl->dev,
> + "failed to disable DC%d stream%d pixel link sync: %d\n",
> + pl->dc_id, pl->stream_id, ret);
> +
> + return ret;
> +}
> +
> +static void imx8qxp_pixel_link_set_mst_addr(struct imx8qxp_pixel_link *pl)
> +{
> + int ret;
> +
> + ret = imx_sc_misc_set_control(pl->ipc_handle,
> + pl->sink_rsc, pl->mst_addr_ctrl,
> + pl->mst_addr);
> + if (ret)
> + DRM_DEV_ERROR(pl->dev,
> + "failed to set DC%d stream%d pixel link mst addr(%u): %d\n",
> + pl->dc_id, pl->stream_id, pl->mst_addr, ret);
> +}
> +
> +static int imx8qxp_pixel_link_bridge_attach(struct drm_bridge *bridge,
> + enum drm_bridge_attach_flags flags)
> +{
> + struct imx8qxp_pixel_link *pl = bridge->driver_private;
> +
> + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
> + DRM_DEV_ERROR(pl->dev,
> + "do not support creating a drm_connector\n");
> + return -EINVAL;
> + }
> +
> + if (!bridge->encoder) {
> + DRM_DEV_ERROR(pl->dev, "missing encoder\n");
> + return -ENODEV;
> + }
> +
> + return drm_bridge_attach(bridge->encoder,
> + pl->next_bridge, bridge,
> + DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> +}
> +
> +static void
> +imx8qxp_pixel_link_bridge_mode_set(struct drm_bridge *bridge,
> + const struct drm_display_mode *mode,
> + const struct drm_display_mode *adjusted_mode)
> +{
> + struct imx8qxp_pixel_link *pl = bridge->driver_private;
> +
> + imx8qxp_pixel_link_set_mst_addr(pl);
> +}
> +
> +static void imx8qxp_pixel_link_bridge_atomic_enable(struct drm_bridge *bridge,
> + struct drm_bridge_state *old_bridge_state)
> +{
> + struct imx8qxp_pixel_link *pl = bridge->driver_private;
> +
> + imx8qxp_pixel_link_enable_mst_en(pl);
> + imx8qxp_pixel_link_enable_mst_vld(pl);
> + imx8qxp_pixel_link_enable_sync(pl);
> +}
> +
> +static void imx8qxp_pixel_link_bridge_atomic_disable(struct drm_bridge *bridge,
> + struct drm_bridge_state *old_bridge_state)
> +{
> + struct imx8qxp_pixel_link *pl = bridge->driver_private;
> +
> + imx8qxp_pixel_link_disable_mst_en(pl);
> + imx8qxp_pixel_link_disable_mst_vld(pl);
> + imx8qxp_pixel_link_disable_sync(pl);
> +}
> +
> +static const u32 imx8qxp_pixel_link_bus_output_fmts[] = {
> + MEDIA_BUS_FMT_RGB888_1X36_CPADLO,
> + MEDIA_BUS_FMT_RGB666_1X36_CPADLO,
> +};
> +
> +static bool imx8qxp_pixel_link_bus_output_fmt_supported(u32 fmt)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts); i++) {
> + if (imx8qxp_pixel_link_bus_output_fmts[i] == fmt)
> + return true;
> + }
> +
> + return false;
> +}
> +
> +static u32 *
> +imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
> + struct drm_bridge_state *bridge_state,
> + struct drm_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state,
> + u32 output_fmt,
> + unsigned int *num_input_fmts)
> +{
> + u32 *input_fmts;
> +
> + if (!imx8qxp_pixel_link_bus_output_fmt_supported(output_fmt))
> + return NULL;
> +
> + *num_input_fmts = 1;
> +
> + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
> + if (!input_fmts)
> + return NULL;
> +
> + input_fmts[0] = output_fmt;
> +
> + return input_fmts;
> +}
> +
> +static u32 *
> +imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
> + struct drm_bridge_state *bridge_state,
> + struct drm_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state,
> + unsigned int *num_output_fmts)
> +{
> + *num_output_fmts = ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts);
> + return kmemdup(imx8qxp_pixel_link_bus_output_fmts,
> + sizeof(imx8qxp_pixel_link_bus_output_fmts), GFP_KERNEL);
> +}
> +
> +static const struct drm_bridge_funcs imx8qxp_pixel_link_bridge_funcs = {
> + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> + .atomic_reset = drm_atomic_helper_bridge_reset,
> + .attach = imx8qxp_pixel_link_bridge_attach,
> + .mode_set = imx8qxp_pixel_link_bridge_mode_set,
> + .atomic_enable = imx8qxp_pixel_link_bridge_atomic_enable,
> + .atomic_disable = imx8qxp_pixel_link_bridge_atomic_disable,
> + .atomic_get_input_bus_fmts =
> + imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts,
> + .atomic_get_output_bus_fmts =
> + imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts,
> +};
> +
> +static int imx8qxp_pixel_link_disable_all_controls(struct imx8qxp_pixel_link *pl)
> +{
> + int ret;
> +
> + ret = imx8qxp_pixel_link_disable_mst_en(pl);
> + if (ret)
> + return ret;
> +
> + ret = imx8qxp_pixel_link_disable_mst_vld(pl);
> + if (ret)
> + return ret;
> +
> + return imx8qxp_pixel_link_disable_sync(pl);
> +}
> +
> +static struct drm_bridge *
> +imx8qxp_pixel_link_find_next_bridge(struct imx8qxp_pixel_link *pl)
> +{
> + struct device_node *np = pl->dev->of_node;
> + struct device_node *port, *remote;
> + struct drm_bridge *next_bridge[PL_MAX_NEXT_BRIDGES];
> + u32 port_id;
> + bool found_port = false;
> + int reg, ep_cnt = 0;
> + int bridge_sel = 0; /* select the first next bridge by default */

Is this comment on the wrong line?

> +
> + for (port_id = 1; port_id <= PL_MAX_MST_ADDR + 1; port_id++) {
> + port = of_graph_get_port_by_id(np, port_id);
> + if (!port)
> + continue;
> +
> + if (of_device_is_available(port)) {
> + found_port = true;
> + of_node_put(port);
> + break;
> + }
> +
> + of_node_put(port);
> + }
> +
> + if (!found_port) {
> + DRM_DEV_ERROR(pl->dev, "no available output port\n");
> + return ERR_PTR(-ENODEV);
> + }
> +
> + for (reg = 0; reg < PL_MAX_NEXT_BRIDGES; reg++) {
> + remote = of_graph_get_remote_node(np, port_id, reg);
> + if (!remote)
> + continue;
> +
> + if (!of_device_is_available(remote->parent)) {
> + DRM_DEV_DEBUG(pl->dev,
> + "port%u endpoint%u remote parent is not available\n",
> + port_id, reg);
> + of_node_put(remote);
> + continue;
> + }
> +
> + next_bridge[ep_cnt] = of_drm_find_bridge(remote);
> + if (!next_bridge[ep_cnt]) {
> + of_node_put(remote);
> + return ERR_PTR(-EPROBE_DEFER);
> + }
> +
> + /* specially select the next bridge with companion PXL2DPI */
> + if (of_find_property(remote, "fsl,companion-pxl2dpi", NULL))
> + bridge_sel = ep_cnt;
> +
> + ep_cnt++;
> +
> + of_node_put(remote);
> + }
> +
> + pl->mst_addr = port_id - 1;
> +
> + return next_bridge[bridge_sel];
> +}
> +
> +static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev)
> +{
> + struct imx8qxp_pixel_link *pl;
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + int ret;
> +
> + pl = devm_kzalloc(dev, sizeof(*pl), GFP_KERNEL);
> + if (!pl)
> + return -ENOMEM;
> +
> + ret = imx_scu_get_handle(&pl->ipc_handle);
> + if (ret) {
> + if (ret != -EPROBE_DEFER)
> + DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n",
> + ret);
> + return ret;
> + }
> +
> + pl->id = of_alias_get_id(np, "dc_pl");
> + if (pl->id < 0) {
> + DRM_DEV_ERROR(dev,
> + "failed to get pixel link node alias id: %d\n",
> + pl->id);
> + return pl->id;
> + }
> +
> + pl->dev = dev;
> +
> + pl->dc_id = pl->id / 2;
> + pl->stream_id = pl->id % 2;
> +
> + pl->sink_rsc = pl->dc_id ? IMX_SC_R_DC_1 : IMX_SC_R_DC_0;
> +
> + if (pl->stream_id == 0) {
> + pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST1_ADDR;
> + pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST1_ENB;
> + pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST1_VLD;
> + pl->sync_ctrl = IMX_SC_C_SYNC_CTRL0;
> + } else {
> + pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST2_ADDR;
> + pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST2_ENB;
> + pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST2_VLD;
> + pl->sync_ctrl = IMX_SC_C_SYNC_CTRL1;
> + }
> +
> + /* disable all controls to POR default */
> + ret = imx8qxp_pixel_link_disable_all_controls(pl);
> + if (ret)
> + return ret;
> +
> + pl->next_bridge = imx8qxp_pixel_link_find_next_bridge(pl);
> + if (IS_ERR(pl->next_bridge)) {
> + ret = PTR_ERR(pl->next_bridge);
> + if (ret != -EPROBE_DEFER)
> + DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n",
> + ret);
> + return ret;
> + }
> +
> + platform_set_drvdata(pdev, pl);
> +
> + pl->bridge.driver_private = pl;
> + pl->bridge.funcs = &imx8qxp_pixel_link_bridge_funcs;
> + pl->bridge.of_node = np;
> +
> + drm_bridge_add(&pl->bridge);
> +
> + return ret;
> +}
> +
> +static int imx8qxp_pixel_link_bridge_remove(struct platform_device *pdev)
> +{
> + struct imx8qxp_pixel_link *pl = platform_get_drvdata(pdev);
> +
> + drm_bridge_remove(&pl->bridge);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id imx8qxp_pixel_link_dt_ids[] = {
> + { .compatible = "fsl,imx8qm-dc-pixel-link", },
> + { .compatible = "fsl,imx8qxp-dc-pixel-link", },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, imx8qxp_pixel_link_dt_ids);
> +
> +static struct platform_driver imx8qxp_pixel_link_bridge_driver = {
> + .probe = imx8qxp_pixel_link_bridge_probe,
> + .remove = imx8qxp_pixel_link_bridge_remove,
> + .driver = {
> + .of_match_table = imx8qxp_pixel_link_dt_ids,
> + .name = DRIVER_NAME,
> + },
> +};
> +module_platform_driver(imx8qxp_pixel_link_bridge_driver);
> +
> +MODULE_DESCRIPTION("i.MX8QXP/QM display pixel link bridge driver");
> +MODULE_AUTHOR("Liu Ying <[email protected]>");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:" DRIVER_NAME);
> --
> 2.7.4
>

2021-03-04 08:43:06

by Liu Ying

[permalink] [raw]
Subject: Re: [PATCH v4 07/14] drm/bridge: imx: Add i.MX8qm/qxp display pixel link support

Hi Robert,

On Tue, 2021-03-02 at 14:53 +0100, Robert Foss wrote:
> Hey Liu,
>
> Thanks for submitting this patch.
>
> I only have one comment below. With that addressed, feel free to add my r-b.
>
> Reviewed-by: Robert Foss <[email protected]>

Thanks for reviewing this patch.

>
> On Thu, 18 Feb 2021 at 04:59, Liu Ying <[email protected]> wrote:
> > This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link.
> > The pixel link forms a standard asynchronous linkage between
> > pixel sources(display controller or camera module) and pixel
> > consumers(imaging or displays). It consists of two distinct
> > functions, a pixel transfer function and a control interface.
> >
> > Signed-off-by: Liu Ying <[email protected]>
> > ---
> > v3->v4:
> > * No change.
> >
> > v2->v3:
> > * Drop two macros which help define functions and define them directly.
> > * Properly disable all pixel link controls to POR value by calling
> > imx8qxp_pixel_link_disable_all_controls() from
> > imx8qxp_pixel_link_bridge_probe().
> >
> > v1->v2:
> > * Rewrite the function to find the next bridge by properly using OF APIs
> > and dropping unnecessary DT validation. (Rob)
> >
> > drivers/gpu/drm/bridge/imx/Kconfig | 8 +
> > drivers/gpu/drm/bridge/imx/Makefile | 1 +
> > drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 426 ++++++++++++++++++++++++
> > 3 files changed, 435 insertions(+)
> > create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
> >
> > diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
> > index f1c91b6..4d1f027 100644
> > --- a/drivers/gpu/drm/bridge/imx/Kconfig
> > +++ b/drivers/gpu/drm/bridge/imx/Kconfig
> > @@ -6,3 +6,11 @@ config DRM_IMX8QXP_PIXEL_COMBINER
> > help
> > Choose this to enable pixel combiner found in
> > Freescale i.MX8qm/qxp processors.
> > +
> > +config DRM_IMX8QXP_PIXEL_LINK
> > + tristate "Freescale i.MX8QM/QXP display pixel link"
> > + depends on OF
> > + select DRM_KMS_HELPER
> > + help
> > + Choose this to enable display pixel link found in
> > + Freescale i.MX8qm/qxp processors.
> > diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
> > index 7d7c8d6..c15469f 100644
> > --- a/drivers/gpu/drm/bridge/imx/Makefile
> > +++ b/drivers/gpu/drm/bridge/imx/Makefile
> > @@ -1 +1,2 @@
> > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
> > +obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
> > diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
> > new file mode 100644
> > index 00000000..2e5ba4a
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
> > @@ -0,0 +1,426 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +
> > +/*
> > + * Copyright 2020 NXP
> > + */
> > +
> > +#include <linux/firmware/imx/svc/misc.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_graph.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include <drm/drm_atomic_state_helper.h>
> > +#include <drm/drm_bridge.h>
> > +#include <drm/drm_print.h>
> > +
> > +#include <dt-bindings/firmware/imx/rsrc.h>
> > +
> > +#define DRIVER_NAME "imx8qxp-display-pixel-link"
> > +#define PL_MAX_MST_ADDR 3
> > +#define PL_MAX_NEXT_BRIDGES 2
> > +
> > +struct imx8qxp_pixel_link {
> > + struct drm_bridge bridge;
> > + struct drm_bridge *next_bridge;
> > + struct device *dev;
> > + struct imx_sc_ipc *ipc_handle;
> > + int id;
> > + int stream_id;
> > + int dc_id;
> > + u32 sink_rsc;
> > + u32 mst_addr;
> > + u8 mst_addr_ctrl;
> > + u8 mst_en_ctrl;
> > + u8 mst_vld_ctrl;
> > + u8 sync_ctrl;
> > +};
> > +
> > +static void imx8qxp_pixel_link_enable_mst_en(struct imx8qxp_pixel_link *pl)
> > +{
> > + int ret;
> > +
> > + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
> > + pl->mst_en_ctrl, true);
> > + if (ret)
> > + DRM_DEV_ERROR(pl->dev,
> > + "failed to enable DC%d stream%d pixel link mst_en: %d\n",
> > + pl->dc_id, pl->stream_id, ret);
> > +}
> > +
> > +static void imx8qxp_pixel_link_enable_mst_vld(struct imx8qxp_pixel_link *pl)
> > +{
> > + int ret;
> > +
> > + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
> > + pl->mst_vld_ctrl, true);
> > + if (ret)
> > + DRM_DEV_ERROR(pl->dev,
> > + "failed to enable DC%d stream%d pixel link mst_vld: %d\n",
> > + pl->dc_id, pl->stream_id, ret);
> > +}
> > +
> > +static void imx8qxp_pixel_link_enable_sync(struct imx8qxp_pixel_link *pl)
> > +{
> > + int ret;
> > +
> > + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
> > + pl->sync_ctrl, true);
> > + if (ret)
> > + DRM_DEV_ERROR(pl->dev,
> > + "failed to enable DC%d stream%d pixel link sync: %d\n",
> > + pl->dc_id, pl->stream_id, ret);
> > +}
> > +
> > +static int imx8qxp_pixel_link_disable_mst_en(struct imx8qxp_pixel_link *pl)
> > +{
> > + int ret;
> > +
> > + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
> > + pl->mst_en_ctrl, false);
> > + if (ret)
> > + DRM_DEV_ERROR(pl->dev,
> > + "failed to disable DC%d stream%d pixel link mst_en: %d\n",
> > + pl->dc_id, pl->stream_id, ret);
> > +
> > + return ret;
> > +}
> > +
> > +static int imx8qxp_pixel_link_disable_mst_vld(struct imx8qxp_pixel_link *pl)
> > +{
> > + int ret;
> > +
> > + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
> > + pl->mst_vld_ctrl, false);
> > + if (ret)
> > + DRM_DEV_ERROR(pl->dev,
> > + "failed to disable DC%d stream%d pixel link mst_vld: %d\n",
> > + pl->dc_id, pl->stream_id, ret);
> > +
> > + return ret;
> > +}
> > +
> > +static int imx8qxp_pixel_link_disable_sync(struct imx8qxp_pixel_link *pl)
> > +{
> > + int ret;
> > +
> > + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
> > + pl->sync_ctrl, false);
> > + if (ret)
> > + DRM_DEV_ERROR(pl->dev,
> > + "failed to disable DC%d stream%d pixel link sync: %d\n",
> > + pl->dc_id, pl->stream_id, ret);
> > +
> > + return ret;
> > +}
> > +
> > +static void imx8qxp_pixel_link_set_mst_addr(struct imx8qxp_pixel_link *pl)
> > +{
> > + int ret;
> > +
> > + ret = imx_sc_misc_set_control(pl->ipc_handle,
> > + pl->sink_rsc, pl->mst_addr_ctrl,
> > + pl->mst_addr);
> > + if (ret)
> > + DRM_DEV_ERROR(pl->dev,
> > + "failed to set DC%d stream%d pixel link mst addr(%u): %d\n",
> > + pl->dc_id, pl->stream_id, pl->mst_addr, ret);
> > +}
> > +
> > +static int imx8qxp_pixel_link_bridge_attach(struct drm_bridge *bridge,
> > + enum drm_bridge_attach_flags flags)
> > +{
> > + struct imx8qxp_pixel_link *pl = bridge->driver_private;
> > +
> > + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
> > + DRM_DEV_ERROR(pl->dev,
> > + "do not support creating a drm_connector\n");
> > + return -EINVAL;
> > + }
> > +
> > + if (!bridge->encoder) {
> > + DRM_DEV_ERROR(pl->dev, "missing encoder\n");
> > + return -ENODEV;
> > + }
> > +
> > + return drm_bridge_attach(bridge->encoder,
> > + pl->next_bridge, bridge,
> > + DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> > +}
> > +
> > +static void
> > +imx8qxp_pixel_link_bridge_mode_set(struct drm_bridge *bridge,
> > + const struct drm_display_mode *mode,
> > + const struct drm_display_mode *adjusted_mode)
> > +{
> > + struct imx8qxp_pixel_link *pl = bridge->driver_private;
> > +
> > + imx8qxp_pixel_link_set_mst_addr(pl);
> > +}
> > +
> > +static void imx8qxp_pixel_link_bridge_atomic_enable(struct drm_bridge *bridge,
> > + struct drm_bridge_state *old_bridge_state)
> > +{
> > + struct imx8qxp_pixel_link *pl = bridge->driver_private;
> > +
> > + imx8qxp_pixel_link_enable_mst_en(pl);
> > + imx8qxp_pixel_link_enable_mst_vld(pl);
> > + imx8qxp_pixel_link_enable_sync(pl);
> > +}
> > +
> > +static void imx8qxp_pixel_link_bridge_atomic_disable(struct drm_bridge *bridge,
> > + struct drm_bridge_state *old_bridge_state)
> > +{
> > + struct imx8qxp_pixel_link *pl = bridge->driver_private;
> > +
> > + imx8qxp_pixel_link_disable_mst_en(pl);
> > + imx8qxp_pixel_link_disable_mst_vld(pl);
> > + imx8qxp_pixel_link_disable_sync(pl);
> > +}
> > +
> > +static const u32 imx8qxp_pixel_link_bus_output_fmts[] = {
> > + MEDIA_BUS_FMT_RGB888_1X36_CPADLO,
> > + MEDIA_BUS_FMT_RGB666_1X36_CPADLO,
> > +};
> > +
> > +static bool imx8qxp_pixel_link_bus_output_fmt_supported(u32 fmt)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts); i++) {
> > + if (imx8qxp_pixel_link_bus_output_fmts[i] == fmt)
> > + return true;
> > + }
> > +
> > + return false;
> > +}
> > +
> > +static u32 *
> > +imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
> > + struct drm_bridge_state *bridge_state,
> > + struct drm_crtc_state *crtc_state,
> > + struct drm_connector_state *conn_state,
> > + u32 output_fmt,
> > + unsigned int *num_input_fmts)
> > +{
> > + u32 *input_fmts;
> > +
> > + if (!imx8qxp_pixel_link_bus_output_fmt_supported(output_fmt))
> > + return NULL;
> > +
> > + *num_input_fmts = 1;
> > +
> > + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
> > + if (!input_fmts)
> > + return NULL;
> > +
> > + input_fmts[0] = output_fmt;
> > +
> > + return input_fmts;
> > +}
> > +
> > +static u32 *
> > +imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
> > + struct drm_bridge_state *bridge_state,
> > + struct drm_crtc_state *crtc_state,
> > + struct drm_connector_state *conn_state,
> > + unsigned int *num_output_fmts)
> > +{
> > + *num_output_fmts = ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts);
> > + return kmemdup(imx8qxp_pixel_link_bus_output_fmts,
> > + sizeof(imx8qxp_pixel_link_bus_output_fmts), GFP_KERNEL);
> > +}
> > +
> > +static const struct drm_bridge_funcs imx8qxp_pixel_link_bridge_funcs = {
> > + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> > + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> > + .atomic_reset = drm_atomic_helper_bridge_reset,
> > + .attach = imx8qxp_pixel_link_bridge_attach,
> > + .mode_set = imx8qxp_pixel_link_bridge_mode_set,
> > + .atomic_enable = imx8qxp_pixel_link_bridge_atomic_enable,
> > + .atomic_disable = imx8qxp_pixel_link_bridge_atomic_disable,
> > + .atomic_get_input_bus_fmts =
> > + imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts,
> > + .atomic_get_output_bus_fmts =
> > + imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts,
> > +};
> > +
> > +static int imx8qxp_pixel_link_disable_all_controls(struct imx8qxp_pixel_link *pl)
> > +{
> > + int ret;
> > +
> > + ret = imx8qxp_pixel_link_disable_mst_en(pl);
> > + if (ret)
> > + return ret;
> > +
> > + ret = imx8qxp_pixel_link_disable_mst_vld(pl);
> > + if (ret)
> > + return ret;
> > +
> > + return imx8qxp_pixel_link_disable_sync(pl);
> > +}
> > +
> > +static struct drm_bridge *
> > +imx8qxp_pixel_link_find_next_bridge(struct imx8qxp_pixel_link *pl)
> > +{
> > + struct device_node *np = pl->dev->of_node;
> > + struct device_node *port, *remote;
> > + struct drm_bridge *next_bridge[PL_MAX_NEXT_BRIDGES];
> > + u32 port_id;
> > + bool found_port = false;
> > + int reg, ep_cnt = 0;
> > + int bridge_sel = 0; /* select the first next bridge by default */
>
> Is this comment on the wrong line?

I'll make this comment occupy a line just prior to this line in the
next version.

Thanks,
Liu Ying

>
> > +
> > + for (port_id = 1; port_id <= PL_MAX_MST_ADDR + 1; port_id++) {
> > + port = of_graph_get_port_by_id(np, port_id);
> > + if (!port)
> > + continue;
> > +
> > + if (of_device_is_available(port)) {
> > + found_port = true;
> > + of_node_put(port);
> > + break;
> > + }
> > +
> > + of_node_put(port);
> > + }
> > +
> > + if (!found_port) {
> > + DRM_DEV_ERROR(pl->dev, "no available output port\n");
> > + return ERR_PTR(-ENODEV);
> > + }
> > +
> > + for (reg = 0; reg < PL_MAX_NEXT_BRIDGES; reg++) {
> > + remote = of_graph_get_remote_node(np, port_id, reg);
> > + if (!remote)
> > + continue;
> > +
> > + if (!of_device_is_available(remote->parent)) {
> > + DRM_DEV_DEBUG(pl->dev,
> > + "port%u endpoint%u remote parent is not available\n",
> > + port_id, reg);
> > + of_node_put(remote);
> > + continue;
> > + }
> > +
> > + next_bridge[ep_cnt] = of_drm_find_bridge(remote);
> > + if (!next_bridge[ep_cnt]) {
> > + of_node_put(remote);
> > + return ERR_PTR(-EPROBE_DEFER);
> > + }
> > +
> > + /* specially select the next bridge with companion PXL2DPI */
> > + if (of_find_property(remote, "fsl,companion-pxl2dpi", NULL))
> > + bridge_sel = ep_cnt;
> > +
> > + ep_cnt++;
> > +
> > + of_node_put(remote);
> > + }
> > +
> > + pl->mst_addr = port_id - 1;
> > +
> > + return next_bridge[bridge_sel];
> > +}
> > +
> > +static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev)
> > +{
> > + struct imx8qxp_pixel_link *pl;
> > + struct device *dev = &pdev->dev;
> > + struct device_node *np = dev->of_node;
> > + int ret;
> > +
> > + pl = devm_kzalloc(dev, sizeof(*pl), GFP_KERNEL);
> > + if (!pl)
> > + return -ENOMEM;
> > +
> > + ret = imx_scu_get_handle(&pl->ipc_handle);
> > + if (ret) {
> > + if (ret != -EPROBE_DEFER)
> > + DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n",
> > + ret);
> > + return ret;
> > + }
> > +
> > + pl->id = of_alias_get_id(np, "dc_pl");
> > + if (pl->id < 0) {
> > + DRM_DEV_ERROR(dev,
> > + "failed to get pixel link node alias id: %d\n",
> > + pl->id);
> > + return pl->id;
> > + }
> > +
> > + pl->dev = dev;
> > +
> > + pl->dc_id = pl->id / 2;
> > + pl->stream_id = pl->id % 2;
> > +
> > + pl->sink_rsc = pl->dc_id ? IMX_SC_R_DC_1 : IMX_SC_R_DC_0;
> > +
> > + if (pl->stream_id == 0) {
> > + pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST1_ADDR;
> > + pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST1_ENB;
> > + pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST1_VLD;
> > + pl->sync_ctrl = IMX_SC_C_SYNC_CTRL0;
> > + } else {
> > + pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST2_ADDR;
> > + pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST2_ENB;
> > + pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST2_VLD;
> > + pl->sync_ctrl = IMX_SC_C_SYNC_CTRL1;
> > + }
> > +
> > + /* disable all controls to POR default */
> > + ret = imx8qxp_pixel_link_disable_all_controls(pl);
> > + if (ret)
> > + return ret;
> > +
> > + pl->next_bridge = imx8qxp_pixel_link_find_next_bridge(pl);
> > + if (IS_ERR(pl->next_bridge)) {
> > + ret = PTR_ERR(pl->next_bridge);
> > + if (ret != -EPROBE_DEFER)
> > + DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n",
> > + ret);
> > + return ret;
> > + }
> > +
> > + platform_set_drvdata(pdev, pl);
> > +
> > + pl->bridge.driver_private = pl;
> > + pl->bridge.funcs = &imx8qxp_pixel_link_bridge_funcs;
> > + pl->bridge.of_node = np;
> > +
> > + drm_bridge_add(&pl->bridge);
> > +
> > + return ret;
> > +}
> > +
> > +static int imx8qxp_pixel_link_bridge_remove(struct platform_device *pdev)
> > +{
> > + struct imx8qxp_pixel_link *pl = platform_get_drvdata(pdev);
> > +
> > + drm_bridge_remove(&pl->bridge);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id imx8qxp_pixel_link_dt_ids[] = {
> > + { .compatible = "fsl,imx8qm-dc-pixel-link", },
> > + { .compatible = "fsl,imx8qxp-dc-pixel-link", },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, imx8qxp_pixel_link_dt_ids);
> > +
> > +static struct platform_driver imx8qxp_pixel_link_bridge_driver = {
> > + .probe = imx8qxp_pixel_link_bridge_probe,
> > + .remove = imx8qxp_pixel_link_bridge_remove,
> > + .driver = {
> > + .of_match_table = imx8qxp_pixel_link_dt_ids,
> > + .name = DRIVER_NAME,
> > + },
> > +};
> > +module_platform_driver(imx8qxp_pixel_link_bridge_driver);
> > +
> > +MODULE_DESCRIPTION("i.MX8QXP/QM display pixel link bridge driver");
> > +MODULE_AUTHOR("Liu Ying <[email protected]>");
> > +MODULE_LICENSE("GPL v2");
> > +MODULE_ALIAS("platform:" DRIVER_NAME);
> > --
> > 2.7.4
> >

2021-03-04 08:54:25

by Liu Ying

[permalink] [raw]
Subject: Re: [PATCH v4 10/14] drm/bridge: imx: Add LDB driver helper support

Hi Robert,

On Tue, 2021-03-02 at 15:22 +0100, Robert Foss wrote:
> Hey Liu,
>
> Thanks for submitting this patch.

Thanks for reviewing this patch.

>
> On Thu, 18 Feb 2021 at 04:59, Liu Ying <[email protected]> wrote:
> > This patch adds a helper to support LDB drm bridge drivers for
> > i.MX SoCs. Helper functions exported from this driver should
> > implement common logics for all LDB modules embedded in i.MX SoCs.
> >
> > Signed-off-by: Liu Ying <[email protected]>
> > ---
> > v3->v4:
> > * No change.
> >
> > v2->v3:
> > * Call syscon_node_to_regmap() to get regmap instead of
> > syscon_regmap_lookup_by_phandle().
> >
> > v1->v2:
> > * No change.
> >
> > drivers/gpu/drm/bridge/imx/Kconfig | 8 +
> > drivers/gpu/drm/bridge/imx/Makefile | 1 +
> > drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 248 ++++++++++++++++++++++++++++
> > include/drm/bridge/imx_ldb_helper.h | 98 +++++++++++
> > 4 files changed, 355 insertions(+)
> > create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
> > create mode 100644 include/drm/bridge/imx_ldb_helper.h
> >
> > diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
> > index 1ea1ce7..23e24fd 100644
> > --- a/drivers/gpu/drm/bridge/imx/Kconfig
> > +++ b/drivers/gpu/drm/bridge/imx/Kconfig
> > @@ -1,3 +1,11 @@
> > +config DRM_IMX_LVDS_BRIDGE_HELPER
> > + tristate "Freescale i.MX LVDS display bridge helper"
> > + depends on OF
> > + select DRM_PANEL_BRIDGE
> > + help
> > + Helper to support Freescale i.MX LVDS Display Bridge(LDB).
> > + This bridge is embedded in a SoC.
> > +
> > config DRM_IMX8QXP_PIXEL_COMBINER
> > tristate "Freescale i.MX8QM/QXP pixel combiner"
> > depends on OF
> > diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
> > index e74dd64..902b703 100644
> > --- a/drivers/gpu/drm/bridge/imx/Makefile
> > +++ b/drivers/gpu/drm/bridge/imx/Makefile
> > @@ -1,3 +1,4 @@
> > +obj-$(CONFIG_DRM_IMX_LVDS_BRIDGE_HELPER) += imx-ldb-helper.o
> > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
> > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
> > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
> > diff --git a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
> > new file mode 100644
> > index 00000000..94d7f9e
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
> > @@ -0,0 +1,248 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2012 Sascha Hauer, Pengutronix
> > + * Copyright 2019,2020 NXP
> > + */
> > +
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/regmap.h>
> > +
> > +#include <drm/bridge/imx_ldb_helper.h>
> > +#include <drm/drm_of.h>
> > +#include <drm/drm_panel.h>
> > +#include <drm/drm_print.h>
> > +
> > +bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch)
> > +{
> > + return ldb_ch->link_type == LDB_CH_SINGLE_LINK;
> > +}
> > +EXPORT_SYMBOL_GPL(ldb_channel_is_single_link);
> > +
> > +bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch)
> > +{
> > + return ldb_ch->link_type == LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS ||
> > + ldb_ch->link_type == LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS;
> > +}
> > +EXPORT_SYMBOL_GPL(ldb_channel_is_split_link);
> > +
> > +int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
> > + struct drm_bridge_state *bridge_state,
> > + struct drm_crtc_state *crtc_state,
> > + struct drm_connector_state *conn_state)
> > +{
> > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > +
> > + ldb_ch->in_bus_format = bridge_state->input_bus_cfg.format;
> > + ldb_ch->out_bus_format = bridge_state->output_bus_cfg.format;
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(ldb_bridge_atomic_check_helper);
> > +
> > +void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
> > + const struct drm_display_mode *mode,
> > + const struct drm_display_mode *adjusted_mode)
> > +{
> > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > + struct ldb *ldb = ldb_ch->ldb;
> > + bool is_split = ldb_channel_is_split_link(ldb_ch);
> > +
> > + if (is_split)
> > + ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
> > +
> > + switch (ldb_ch->out_bus_format) {
> > + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
> > + break;
> > + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
> > + if (ldb_ch->chno == 0 || is_split)
> > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
> > + if (ldb_ch->chno == 1 || is_split)
> > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
> > + break;
> > + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
> > + if (ldb_ch->chno == 0 || is_split)
> > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
> > + LDB_BIT_MAP_CH0_JEIDA;
> > + if (ldb_ch->chno == 1 || is_split)
> > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
> > + LDB_BIT_MAP_CH1_JEIDA;
> > + break;
> > + }
> > +}
> > +EXPORT_SYMBOL_GPL(ldb_bridge_mode_set_helper);
> > +
> > +void ldb_bridge_enable_helper(struct drm_bridge *bridge)
> > +{
> > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > + struct ldb *ldb = ldb_ch->ldb;
> > +
> > + /*
> > + * Platform specific bridge drivers should set ldb_ctrl properly
> > + * for the enablement, so just write the ctrl_reg here.
> > + */
> > + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
> > +}
> > +EXPORT_SYMBOL_GPL(ldb_bridge_enable_helper);
> > +
> > +void ldb_bridge_disable_helper(struct drm_bridge *bridge)
> > +{
> > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > + struct ldb *ldb = ldb_ch->ldb;
> > + bool is_split = ldb_channel_is_split_link(ldb_ch);
> > +
> > + if (ldb_ch->chno == 0 || is_split)
> > + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
> > + if (ldb_ch->chno == 1 || is_split)
> > + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
> > +
> > + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
> > +}
> > +EXPORT_SYMBOL_GPL(ldb_bridge_disable_helper);
> > +
> > +int ldb_bridge_attach_helper(struct drm_bridge *bridge,
> > + enum drm_bridge_attach_flags flags)
> > +{
> > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > + struct ldb *ldb = ldb_ch->ldb;
> > +
> > + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
> > + DRM_DEV_ERROR(ldb->dev,
> > + "do not support creating a drm_connector\n");
> > + return -EINVAL;
> > + }
> > +
> > + if (!bridge->encoder) {
> > + DRM_DEV_ERROR(ldb->dev, "missing encoder\n");
> > + return -ENODEV;
> > + }
> > +
> > + return drm_bridge_attach(bridge->encoder,
> > + ldb_ch->next_bridge, bridge,
> > + DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> > +}
> > +EXPORT_SYMBOL_GPL(ldb_bridge_attach_helper);
> > +
> > +int ldb_init_helper(struct ldb *ldb)
> > +{
> > + struct device *dev = ldb->dev;
> > + struct device_node *np = dev->of_node;
> > + struct device_node *child;
> > + int ret;
> > + u32 i;
> > +
> > + ldb->regmap = syscon_node_to_regmap(np->parent);
> > + if (IS_ERR(ldb->regmap)) {
> > + ret = PTR_ERR(ldb->regmap);
> > + if (ret != -EPROBE_DEFER)
> > + DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret);
> > + return ret;
> > + }
> > +
> > + for_each_available_child_of_node(np, child) {
> > + struct ldb_channel *ldb_ch;
> > +
> > + ret = of_property_read_u32(child, "reg", &i);
> > + if (ret || i > MAX_LDB_CHAN_NUM - 1) {
> > + ret = -EINVAL;
> > + DRM_DEV_ERROR(dev,
> > + "invalid channel node address: %u\n", i);
> > + of_node_put(child);
> > + return ret;
> > + }
> > +
> > + ldb_ch = ldb->channel[i];
> > + ldb_ch->ldb = ldb;
> > + ldb_ch->chno = i;
> > + ldb_ch->is_available = true;
> > + ldb_ch->np = child;
> > +
> > + ldb->available_ch_cnt++;
> > + }
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(ldb_init_helper);
> > +
> > +int ldb_find_next_bridge_helper(struct ldb *ldb)
> > +{
> > + struct device *dev = ldb->dev;
> > + struct ldb_channel *ldb_ch;
> > + int ret, i;
> > +
> > + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
> > + ldb_ch = ldb->channel[i];
> > +
> > + if (!ldb_ch->is_available)
> > + continue;
> > +
> > + ret = drm_of_find_panel_or_bridge(ldb_ch->np, 1, 0,
> > + &ldb_ch->panel,
> > + &ldb_ch->next_bridge);
> > + if (ret) {
> > + if (ret != -EPROBE_DEFER)
> > + DRM_DEV_ERROR(dev,
> > + "failed to find panel or bridge: %d\n",
> > + ret);
> > + return ret;
> > + }
> > +
> > + if (ldb_ch->panel) {
> > + ldb_ch->next_bridge = devm_drm_panel_bridge_add(dev,
> > + ldb_ch->panel);
> > + if (IS_ERR(ldb_ch->next_bridge)) {
> > + ret = PTR_ERR(ldb_ch->next_bridge);
> > + DRM_DEV_ERROR(dev,
> > + "failed to add panel bridge: %d\n",
> > + ret);
> > + return ret;
> > + }
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(ldb_find_next_bridge_helper);
> > +
> > +void ldb_add_bridge_helper(struct ldb *ldb,
> > + const struct drm_bridge_funcs *bridge_funcs)
> > +{
> > + struct ldb_channel *ldb_ch;
> > + int i;
> > +
> > + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
> > + ldb_ch = ldb->channel[i];
> > +
> > + if (!ldb_ch->is_available)
> > + continue;
> > +
> > + ldb_ch->bridge.driver_private = ldb_ch;
> > + ldb_ch->bridge.funcs = bridge_funcs;
> > + ldb_ch->bridge.of_node = ldb_ch->np;
> > +
> > + drm_bridge_add(&ldb_ch->bridge);
> > + }
> > +}
> > +EXPORT_SYMBOL_GPL(ldb_add_bridge_helper);
> > +
> > +void ldb_remove_bridge_helper(struct ldb *ldb)
> > +{
> > + struct ldb_channel *ldb_ch;
> > + int i;
> > +
> > + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
> > + ldb_ch = ldb->channel[i];
> > +
> > + if (!ldb_ch->is_available)
> > + continue;
> > +
> > + drm_bridge_remove(&ldb_ch->bridge);
> > + }
> > +}
> > +EXPORT_SYMBOL_GPL(ldb_remove_bridge_helper);
> > +
> > +MODULE_DESCRIPTION("Freescale i.MX LVDS Display Bridge driver helper");
> > +MODULE_AUTHOR("Liu Ying <[email protected]>");
> > +MODULE_LICENSE("GPL v2");
> > +MODULE_ALIAS("platform:imx-ldb-helper");
>
> I'm not entirely sure why this set of helper functions should be a
> module. It's not a driver, but rather a toolbox for the LDB driver,
> which is fine, but there is no situation I can see where this module
> would be unloaded and the LDB driver would be loaded.

I can see drivers/gpu/drm/drm_mipi_dbi.c is also a module and
essentially provides helpers to MIPI DBI drivers, but it is not a
driver. I don't see this imx-ldb-helper can be anything else other
than a module.

Or, do you mean that imx-ldb-helper should be only built-in?

>
> > diff --git a/include/drm/bridge/imx_ldb_helper.h b/include/drm/bridge/imx_ldb_helper.h
> > new file mode 100644
> > index 00000000..2a7ba97
> > --- /dev/null
> > +++ b/include/drm/bridge/imx_ldb_helper.h
>
> This header is specific to this driver, and I would expect it to not
> be useful to other drivers. Additionally the filename has a different
> format than the .c file it corresponds to. I would change the name and
> path to "drivers/gpu/drm/bridge/imx/imx-ldb-helper.h".

The i.MX53/6qdl LDB driver(drivers/gpu/drm/imx/imx-ldb.c) can
potentially use this header, but it's a DRM encoder driver.
So, maybe, it's a good idea to move this header to the 'drivers' folder
and rename it to 'imx-ldb-helper.h' ofc. If no objections, I'll do as
what you're suggesting here in the next version.

Regards,
Liu Ying

>
> > @@ -0,0 +1,98 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +
> > +/*
> > + * Copyright 2019,2020 NXP
> > + */
> > +
> > +#ifndef __FSL_IMX_LDB__
> > +#define __FSL_IMX_LDB__
> > +
> > +#include <linux/device.h>
> > +#include <linux/kernel.h>
> > +#include <linux/of.h>
> > +#include <linux/regmap.h>
> > +
> > +#include <drm/drm_atomic.h>
> > +#include <drm/drm_bridge.h>
> > +#include <drm/drm_device.h>
> > +#include <drm/drm_encoder.h>
> > +#include <drm/drm_modeset_helper_vtables.h>
> > +#include <drm/drm_panel.h>
> > +
> > +#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
> > +#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
> > +#define LDB_CH0_MODE_EN_MASK (3 << 0)
> > +#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
> > +#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
> > +#define LDB_CH1_MODE_EN_MASK (3 << 2)
> > +#define LDB_SPLIT_MODE_EN (1 << 4)
> > +#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
> > +#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
> > +#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
> > +#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
> > +#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
> > +#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
> > +
> > +#define MAX_LDB_CHAN_NUM 2
> > +
> > +enum ldb_channel_link_type {
> > + LDB_CH_SINGLE_LINK,
> > + LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS,
> > + LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS,
> > +};
> > +
> > +struct ldb;
> > +
> > +struct ldb_channel {
> > + struct ldb *ldb;
> > + struct drm_bridge bridge;
> > + struct drm_panel *panel;
> > + struct drm_bridge *next_bridge;
> > + struct device_node *np;
> > + u32 chno;
> > + bool is_available;
> > + u32 in_bus_format;
> > + u32 out_bus_format;
> > + enum ldb_channel_link_type link_type;
> > +};
> > +
> > +struct ldb {
> > + struct regmap *regmap;
> > + struct device *dev;
> > + struct ldb_channel *channel[MAX_LDB_CHAN_NUM];
> > + unsigned int ctrl_reg;
> > + u32 ldb_ctrl;
> > + unsigned int available_ch_cnt;
> > +};
> > +
> > +#define bridge_to_ldb_ch(b) container_of(b, struct ldb_channel, bridge)
> > +
> > +bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch);
> > +bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch);
> > +
> > +int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
> > + struct drm_bridge_state *bridge_state,
> > + struct drm_crtc_state *crtc_state,
> > + struct drm_connector_state *conn_state);
> > +
> > +void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
> > + const struct drm_display_mode *mode,
> > + const struct drm_display_mode *adjusted_mode);
> > +
> > +void ldb_bridge_enable_helper(struct drm_bridge *bridge);
> > +
> > +void ldb_bridge_disable_helper(struct drm_bridge *bridge);
> > +
> > +int ldb_bridge_attach_helper(struct drm_bridge *bridge,
> > + enum drm_bridge_attach_flags flags);
> > +
> > +int ldb_init_helper(struct ldb *ldb);
> > +
> > +int ldb_find_next_bridge_helper(struct ldb *ldb);
> > +
> > +void ldb_add_bridge_helper(struct ldb *ldb,
> > + const struct drm_bridge_funcs *bridge_funcs);
> > +
> > +void ldb_remove_bridge_helper(struct ldb *ldb);
> > +
> > +#endif /* __FSL_IMX_LDB__ */
> > --
> > 2.7.4
> >

2021-03-04 11:51:45

by Robert Foss

[permalink] [raw]
Subject: Re: [PATCH v4 10/14] drm/bridge: imx: Add LDB driver helper support

On Wed, 3 Mar 2021 at 08:23, Liu Ying <[email protected]> wrote:
>
> Hi Robert,
>
> On Tue, 2021-03-02 at 15:22 +0100, Robert Foss wrote:
> > Hey Liu,
> >
> > Thanks for submitting this patch.
>
> Thanks for reviewing this patch.
>
> >
> > On Thu, 18 Feb 2021 at 04:59, Liu Ying <[email protected]> wrote:
> > > This patch adds a helper to support LDB drm bridge drivers for
> > > i.MX SoCs. Helper functions exported from this driver should
> > > implement common logics for all LDB modules embedded in i.MX SoCs.
> > >
> > > Signed-off-by: Liu Ying <[email protected]>
> > > ---
> > > v3->v4:
> > > * No change.
> > >
> > > v2->v3:
> > > * Call syscon_node_to_regmap() to get regmap instead of
> > > syscon_regmap_lookup_by_phandle().
> > >
> > > v1->v2:
> > > * No change.
> > >
> > > drivers/gpu/drm/bridge/imx/Kconfig | 8 +
> > > drivers/gpu/drm/bridge/imx/Makefile | 1 +
> > > drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 248 ++++++++++++++++++++++++++++
> > > include/drm/bridge/imx_ldb_helper.h | 98 +++++++++++
> > > 4 files changed, 355 insertions(+)
> > > create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
> > > create mode 100644 include/drm/bridge/imx_ldb_helper.h
> > >
> > > diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
> > > index 1ea1ce7..23e24fd 100644
> > > --- a/drivers/gpu/drm/bridge/imx/Kconfig
> > > +++ b/drivers/gpu/drm/bridge/imx/Kconfig
> > > @@ -1,3 +1,11 @@
> > > +config DRM_IMX_LVDS_BRIDGE_HELPER
> > > + tristate "Freescale i.MX LVDS display bridge helper"
> > > + depends on OF
> > > + select DRM_PANEL_BRIDGE
> > > + help
> > > + Helper to support Freescale i.MX LVDS Display Bridge(LDB).
> > > + This bridge is embedded in a SoC.
> > > +
> > > config DRM_IMX8QXP_PIXEL_COMBINER
> > > tristate "Freescale i.MX8QM/QXP pixel combiner"
> > > depends on OF
> > > diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
> > > index e74dd64..902b703 100644
> > > --- a/drivers/gpu/drm/bridge/imx/Makefile
> > > +++ b/drivers/gpu/drm/bridge/imx/Makefile
> > > @@ -1,3 +1,4 @@
> > > +obj-$(CONFIG_DRM_IMX_LVDS_BRIDGE_HELPER) += imx-ldb-helper.o
> > > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
> > > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
> > > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
> > > diff --git a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
> > > new file mode 100644
> > > index 00000000..94d7f9e
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
> > > @@ -0,0 +1,248 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright (C) 2012 Sascha Hauer, Pengutronix
> > > + * Copyright 2019,2020 NXP
> > > + */
> > > +
> > > +#include <linux/mfd/syscon.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of.h>
> > > +#include <linux/regmap.h>
> > > +
> > > +#include <drm/bridge/imx_ldb_helper.h>
> > > +#include <drm/drm_of.h>
> > > +#include <drm/drm_panel.h>
> > > +#include <drm/drm_print.h>
> > > +
> > > +bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch)
> > > +{
> > > + return ldb_ch->link_type == LDB_CH_SINGLE_LINK;
> > > +}
> > > +EXPORT_SYMBOL_GPL(ldb_channel_is_single_link);
> > > +
> > > +bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch)
> > > +{
> > > + return ldb_ch->link_type == LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS ||
> > > + ldb_ch->link_type == LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS;
> > > +}
> > > +EXPORT_SYMBOL_GPL(ldb_channel_is_split_link);
> > > +
> > > +int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
> > > + struct drm_bridge_state *bridge_state,
> > > + struct drm_crtc_state *crtc_state,
> > > + struct drm_connector_state *conn_state)
> > > +{
> > > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > > +
> > > + ldb_ch->in_bus_format = bridge_state->input_bus_cfg.format;
> > > + ldb_ch->out_bus_format = bridge_state->output_bus_cfg.format;
> > > +
> > > + return 0;
> > > +}
> > > +EXPORT_SYMBOL_GPL(ldb_bridge_atomic_check_helper);
> > > +
> > > +void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
> > > + const struct drm_display_mode *mode,
> > > + const struct drm_display_mode *adjusted_mode)
> > > +{
> > > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > > + struct ldb *ldb = ldb_ch->ldb;
> > > + bool is_split = ldb_channel_is_split_link(ldb_ch);
> > > +
> > > + if (is_split)
> > > + ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
> > > +
> > > + switch (ldb_ch->out_bus_format) {
> > > + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
> > > + break;
> > > + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
> > > + if (ldb_ch->chno == 0 || is_split)
> > > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
> > > + if (ldb_ch->chno == 1 || is_split)
> > > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
> > > + break;
> > > + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
> > > + if (ldb_ch->chno == 0 || is_split)
> > > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
> > > + LDB_BIT_MAP_CH0_JEIDA;
> > > + if (ldb_ch->chno == 1 || is_split)
> > > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
> > > + LDB_BIT_MAP_CH1_JEIDA;
> > > + break;
> > > + }
> > > +}
> > > +EXPORT_SYMBOL_GPL(ldb_bridge_mode_set_helper);
> > > +
> > > +void ldb_bridge_enable_helper(struct drm_bridge *bridge)
> > > +{
> > > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > > + struct ldb *ldb = ldb_ch->ldb;
> > > +
> > > + /*
> > > + * Platform specific bridge drivers should set ldb_ctrl properly
> > > + * for the enablement, so just write the ctrl_reg here.
> > > + */
> > > + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
> > > +}
> > > +EXPORT_SYMBOL_GPL(ldb_bridge_enable_helper);
> > > +
> > > +void ldb_bridge_disable_helper(struct drm_bridge *bridge)
> > > +{
> > > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > > + struct ldb *ldb = ldb_ch->ldb;
> > > + bool is_split = ldb_channel_is_split_link(ldb_ch);
> > > +
> > > + if (ldb_ch->chno == 0 || is_split)
> > > + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
> > > + if (ldb_ch->chno == 1 || is_split)
> > > + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
> > > +
> > > + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
> > > +}
> > > +EXPORT_SYMBOL_GPL(ldb_bridge_disable_helper);
> > > +
> > > +int ldb_bridge_attach_helper(struct drm_bridge *bridge,
> > > + enum drm_bridge_attach_flags flags)
> > > +{
> > > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > > + struct ldb *ldb = ldb_ch->ldb;
> > > +
> > > + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
> > > + DRM_DEV_ERROR(ldb->dev,
> > > + "do not support creating a drm_connector\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + if (!bridge->encoder) {
> > > + DRM_DEV_ERROR(ldb->dev, "missing encoder\n");
> > > + return -ENODEV;
> > > + }
> > > +
> > > + return drm_bridge_attach(bridge->encoder,
> > > + ldb_ch->next_bridge, bridge,
> > > + DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> > > +}
> > > +EXPORT_SYMBOL_GPL(ldb_bridge_attach_helper);
> > > +
> > > +int ldb_init_helper(struct ldb *ldb)
> > > +{
> > > + struct device *dev = ldb->dev;
> > > + struct device_node *np = dev->of_node;
> > > + struct device_node *child;
> > > + int ret;
> > > + u32 i;
> > > +
> > > + ldb->regmap = syscon_node_to_regmap(np->parent);
> > > + if (IS_ERR(ldb->regmap)) {
> > > + ret = PTR_ERR(ldb->regmap);
> > > + if (ret != -EPROBE_DEFER)
> > > + DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret);
> > > + return ret;
> > > + }
> > > +
> > > + for_each_available_child_of_node(np, child) {
> > > + struct ldb_channel *ldb_ch;
> > > +
> > > + ret = of_property_read_u32(child, "reg", &i);
> > > + if (ret || i > MAX_LDB_CHAN_NUM - 1) {
> > > + ret = -EINVAL;
> > > + DRM_DEV_ERROR(dev,
> > > + "invalid channel node address: %u\n", i);
> > > + of_node_put(child);
> > > + return ret;
> > > + }
> > > +
> > > + ldb_ch = ldb->channel[i];
> > > + ldb_ch->ldb = ldb;
> > > + ldb_ch->chno = i;
> > > + ldb_ch->is_available = true;
> > > + ldb_ch->np = child;
> > > +
> > > + ldb->available_ch_cnt++;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +EXPORT_SYMBOL_GPL(ldb_init_helper);
> > > +
> > > +int ldb_find_next_bridge_helper(struct ldb *ldb)
> > > +{
> > > + struct device *dev = ldb->dev;
> > > + struct ldb_channel *ldb_ch;
> > > + int ret, i;
> > > +
> > > + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
> > > + ldb_ch = ldb->channel[i];
> > > +
> > > + if (!ldb_ch->is_available)
> > > + continue;
> > > +
> > > + ret = drm_of_find_panel_or_bridge(ldb_ch->np, 1, 0,
> > > + &ldb_ch->panel,
> > > + &ldb_ch->next_bridge);
> > > + if (ret) {
> > > + if (ret != -EPROBE_DEFER)
> > > + DRM_DEV_ERROR(dev,
> > > + "failed to find panel or bridge: %d\n",
> > > + ret);
> > > + return ret;
> > > + }
> > > +
> > > + if (ldb_ch->panel) {
> > > + ldb_ch->next_bridge = devm_drm_panel_bridge_add(dev,
> > > + ldb_ch->panel);
> > > + if (IS_ERR(ldb_ch->next_bridge)) {
> > > + ret = PTR_ERR(ldb_ch->next_bridge);
> > > + DRM_DEV_ERROR(dev,
> > > + "failed to add panel bridge: %d\n",
> > > + ret);
> > > + return ret;
> > > + }
> > > + }
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +EXPORT_SYMBOL_GPL(ldb_find_next_bridge_helper);
> > > +
> > > +void ldb_add_bridge_helper(struct ldb *ldb,
> > > + const struct drm_bridge_funcs *bridge_funcs)
> > > +{
> > > + struct ldb_channel *ldb_ch;
> > > + int i;
> > > +
> > > + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
> > > + ldb_ch = ldb->channel[i];
> > > +
> > > + if (!ldb_ch->is_available)
> > > + continue;
> > > +
> > > + ldb_ch->bridge.driver_private = ldb_ch;
> > > + ldb_ch->bridge.funcs = bridge_funcs;
> > > + ldb_ch->bridge.of_node = ldb_ch->np;
> > > +
> > > + drm_bridge_add(&ldb_ch->bridge);
> > > + }
> > > +}
> > > +EXPORT_SYMBOL_GPL(ldb_add_bridge_helper);
> > > +
> > > +void ldb_remove_bridge_helper(struct ldb *ldb)
> > > +{
> > > + struct ldb_channel *ldb_ch;
> > > + int i;
> > > +
> > > + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
> > > + ldb_ch = ldb->channel[i];
> > > +
> > > + if (!ldb_ch->is_available)
> > > + continue;
> > > +
> > > + drm_bridge_remove(&ldb_ch->bridge);
> > > + }
> > > +}
> > > +EXPORT_SYMBOL_GPL(ldb_remove_bridge_helper);
> > > +
> > > +MODULE_DESCRIPTION("Freescale i.MX LVDS Display Bridge driver helper");
> > > +MODULE_AUTHOR("Liu Ying <[email protected]>");
> > > +MODULE_LICENSE("GPL v2");
> > > +MODULE_ALIAS("platform:imx-ldb-helper");
> >
> > I'm not entirely sure why this set of helper functions should be a
> > module. It's not a driver, but rather a toolbox for the LDB driver,
> > which is fine, but there is no situation I can see where this module
> > would be unloaded and the LDB driver would be loaded.
>
> I can see drivers/gpu/drm/drm_mipi_dbi.c is also a module and
> essentially provides helpers to MIPI DBI drivers, but it is not a
> driver. I don't see this imx-ldb-helper can be anything else other
> than a module.
>
> Or, do you mean that imx-ldb-helper should be only built-in?

My thinking was that it should just be linked together with the rest
of the imx8qxp-ldb driver. But this ties in to my next comment.

>
> >
> > > diff --git a/include/drm/bridge/imx_ldb_helper.h b/include/drm/bridge/imx_ldb_helper.h
> > > new file mode 100644
> > > index 00000000..2a7ba97
> > > --- /dev/null
> > > +++ b/include/drm/bridge/imx_ldb_helper.h
> >
> > This header is specific to this driver, and I would expect it to not
> > be useful to other drivers. Additionally the filename has a different
> > format than the .c file it corresponds to. I would change the name and
> > path to "drivers/gpu/drm/bridge/imx/imx-ldb-helper.h".
>
> The i.MX53/6qdl LDB driver(drivers/gpu/drm/imx/imx-ldb.c) can
> potentially use this header, but it's a DRM encoder driver.
> So, maybe, it's a good idea to move this header to the 'drivers' folder
> and rename it to 'imx-ldb-helper.h' ofc. If no objections, I'll do as
> what you're suggesting here in the next version.

Ah I see. If ldb-helper is indeed used by two drivers, making it a
module seems reasonable.

I think we have two options then.

#1 Make imx-ldb-helper an object that is just linked with the
imx8qxp-ldb driver.

#2 Keep imx-ldb-helper as a module, and implement support for using it
in the imx-ldb driver. Ideally I'd like to see the imx-ldb-helper
module patch in the same series as as imx53/6qdl switching to using
the module. These things have a tendency of not happening if not done
right away :)


>
> Regards,
> Liu Ying
>
> >
> > > @@ -0,0 +1,98 @@
> > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > +
> > > +/*
> > > + * Copyright 2019,2020 NXP
> > > + */
> > > +
> > > +#ifndef __FSL_IMX_LDB__
> > > +#define __FSL_IMX_LDB__
> > > +
> > > +#include <linux/device.h>
> > > +#include <linux/kernel.h>
> > > +#include <linux/of.h>
> > > +#include <linux/regmap.h>
> > > +
> > > +#include <drm/drm_atomic.h>
> > > +#include <drm/drm_bridge.h>
> > > +#include <drm/drm_device.h>
> > > +#include <drm/drm_encoder.h>
> > > +#include <drm/drm_modeset_helper_vtables.h>
> > > +#include <drm/drm_panel.h>
> > > +
> > > +#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
> > > +#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
> > > +#define LDB_CH0_MODE_EN_MASK (3 << 0)
> > > +#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
> > > +#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
> > > +#define LDB_CH1_MODE_EN_MASK (3 << 2)
> > > +#define LDB_SPLIT_MODE_EN (1 << 4)
> > > +#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
> > > +#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
> > > +#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
> > > +#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
> > > +#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
> > > +#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
> > > +
> > > +#define MAX_LDB_CHAN_NUM 2
> > > +
> > > +enum ldb_channel_link_type {
> > > + LDB_CH_SINGLE_LINK,
> > > + LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS,
> > > + LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS,
> > > +};
> > > +
> > > +struct ldb;
> > > +
> > > +struct ldb_channel {
> > > + struct ldb *ldb;
> > > + struct drm_bridge bridge;
> > > + struct drm_panel *panel;
> > > + struct drm_bridge *next_bridge;
> > > + struct device_node *np;
> > > + u32 chno;
> > > + bool is_available;
> > > + u32 in_bus_format;
> > > + u32 out_bus_format;
> > > + enum ldb_channel_link_type link_type;
> > > +};
> > > +
> > > +struct ldb {
> > > + struct regmap *regmap;
> > > + struct device *dev;
> > > + struct ldb_channel *channel[MAX_LDB_CHAN_NUM];
> > > + unsigned int ctrl_reg;
> > > + u32 ldb_ctrl;
> > > + unsigned int available_ch_cnt;
> > > +};
> > > +
> > > +#define bridge_to_ldb_ch(b) container_of(b, struct ldb_channel, bridge)
> > > +
> > > +bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch);
> > > +bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch);
> > > +
> > > +int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
> > > + struct drm_bridge_state *bridge_state,
> > > + struct drm_crtc_state *crtc_state,
> > > + struct drm_connector_state *conn_state);
> > > +
> > > +void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
> > > + const struct drm_display_mode *mode,
> > > + const struct drm_display_mode *adjusted_mode);
> > > +
> > > +void ldb_bridge_enable_helper(struct drm_bridge *bridge);
> > > +
> > > +void ldb_bridge_disable_helper(struct drm_bridge *bridge);
> > > +
> > > +int ldb_bridge_attach_helper(struct drm_bridge *bridge,
> > > + enum drm_bridge_attach_flags flags);
> > > +
> > > +int ldb_init_helper(struct ldb *ldb);
> > > +
> > > +int ldb_find_next_bridge_helper(struct ldb *ldb);
> > > +
> > > +void ldb_add_bridge_helper(struct ldb *ldb,
> > > + const struct drm_bridge_funcs *bridge_funcs);
> > > +
> > > +void ldb_remove_bridge_helper(struct ldb *ldb);
> > > +
> > > +#endif /* __FSL_IMX_LDB__ */
> > > --
> > > 2.7.4
> > >
>

2021-03-05 00:01:10

by Liu Ying

[permalink] [raw]
Subject: Re: [PATCH v4 10/14] drm/bridge: imx: Add LDB driver helper support

Hi Robert,

On Wed, 2021-03-03 at 16:34 +0100, Robert Foss wrote:
> On Wed, 3 Mar 2021 at 08:23, Liu Ying <[email protected]> wrote:
> > Hi Robert,
> >
> > On Tue, 2021-03-02 at 15:22 +0100, Robert Foss wrote:
> > > Hey Liu,
> > >
> > > Thanks for submitting this patch.
> >
> > Thanks for reviewing this patch.
> >
> > > On Thu, 18 Feb 2021 at 04:59, Liu Ying <[email protected]> wrote:
> > > > This patch adds a helper to support LDB drm bridge drivers for
> > > > i.MX SoCs. Helper functions exported from this driver should
> > > > implement common logics for all LDB modules embedded in i.MX SoCs.
> > > >
> > > > Signed-off-by: Liu Ying <[email protected]>
> > > > ---
> > > > v3->v4:
> > > > * No change.
> > > >
> > > > v2->v3:
> > > > * Call syscon_node_to_regmap() to get regmap instead of
> > > > syscon_regmap_lookup_by_phandle().
> > > >
> > > > v1->v2:
> > > > * No change.
> > > >
> > > > drivers/gpu/drm/bridge/imx/Kconfig | 8 +
> > > > drivers/gpu/drm/bridge/imx/Makefile | 1 +
> > > > drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 248 ++++++++++++++++++++++++++++
> > > > include/drm/bridge/imx_ldb_helper.h | 98 +++++++++++
> > > > 4 files changed, 355 insertions(+)
> > > > create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
> > > > create mode 100644 include/drm/bridge/imx_ldb_helper.h
> > > >
> > > > diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
> > > > index 1ea1ce7..23e24fd 100644
> > > > --- a/drivers/gpu/drm/bridge/imx/Kconfig
> > > > +++ b/drivers/gpu/drm/bridge/imx/Kconfig
> > > > @@ -1,3 +1,11 @@
> > > > +config DRM_IMX_LVDS_BRIDGE_HELPER
> > > > + tristate "Freescale i.MX LVDS display bridge helper"
> > > > + depends on OF
> > > > + select DRM_PANEL_BRIDGE
> > > > + help
> > > > + Helper to support Freescale i.MX LVDS Display Bridge(LDB).
> > > > + This bridge is embedded in a SoC.
> > > > +
> > > > config DRM_IMX8QXP_PIXEL_COMBINER
> > > > tristate "Freescale i.MX8QM/QXP pixel combiner"
> > > > depends on OF
> > > > diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
> > > > index e74dd64..902b703 100644
> > > > --- a/drivers/gpu/drm/bridge/imx/Makefile
> > > > +++ b/drivers/gpu/drm/bridge/imx/Makefile
> > > > @@ -1,3 +1,4 @@
> > > > +obj-$(CONFIG_DRM_IMX_LVDS_BRIDGE_HELPER) += imx-ldb-helper.o
> > > > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
> > > > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
> > > > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
> > > > diff --git a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
> > > > new file mode 100644
> > > > index 00000000..94d7f9e
> > > > --- /dev/null
> > > > +++ b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
> > > > @@ -0,0 +1,248 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright (C) 2012 Sascha Hauer, Pengutronix
> > > > + * Copyright 2019,2020 NXP
> > > > + */
> > > > +
> > > > +#include <linux/mfd/syscon.h>
> > > > +#include <linux/module.h>
> > > > +#include <linux/of.h>
> > > > +#include <linux/regmap.h>
> > > > +
> > > > +#include <drm/bridge/imx_ldb_helper.h>
> > > > +#include <drm/drm_of.h>
> > > > +#include <drm/drm_panel.h>
> > > > +#include <drm/drm_print.h>
> > > > +
> > > > +bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch)
> > > > +{
> > > > + return ldb_ch->link_type == LDB_CH_SINGLE_LINK;
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(ldb_channel_is_single_link);
> > > > +
> > > > +bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch)
> > > > +{
> > > > + return ldb_ch->link_type == LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS ||
> > > > + ldb_ch->link_type == LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS;
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(ldb_channel_is_split_link);
> > > > +
> > > > +int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
> > > > + struct drm_bridge_state *bridge_state,
> > > > + struct drm_crtc_state *crtc_state,
> > > > + struct drm_connector_state *conn_state)
> > > > +{
> > > > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > > > +
> > > > + ldb_ch->in_bus_format = bridge_state->input_bus_cfg.format;
> > > > + ldb_ch->out_bus_format = bridge_state->output_bus_cfg.format;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(ldb_bridge_atomic_check_helper);
> > > > +
> > > > +void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
> > > > + const struct drm_display_mode *mode,
> > > > + const struct drm_display_mode *adjusted_mode)
> > > > +{
> > > > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > > > + struct ldb *ldb = ldb_ch->ldb;
> > > > + bool is_split = ldb_channel_is_split_link(ldb_ch);
> > > > +
> > > > + if (is_split)
> > > > + ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
> > > > +
> > > > + switch (ldb_ch->out_bus_format) {
> > > > + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
> > > > + break;
> > > > + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
> > > > + if (ldb_ch->chno == 0 || is_split)
> > > > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
> > > > + if (ldb_ch->chno == 1 || is_split)
> > > > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
> > > > + break;
> > > > + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
> > > > + if (ldb_ch->chno == 0 || is_split)
> > > > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
> > > > + LDB_BIT_MAP_CH0_JEIDA;
> > > > + if (ldb_ch->chno == 1 || is_split)
> > > > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
> > > > + LDB_BIT_MAP_CH1_JEIDA;
> > > > + break;
> > > > + }
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(ldb_bridge_mode_set_helper);
> > > > +
> > > > +void ldb_bridge_enable_helper(struct drm_bridge *bridge)
> > > > +{
> > > > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > > > + struct ldb *ldb = ldb_ch->ldb;
> > > > +
> > > > + /*
> > > > + * Platform specific bridge drivers should set ldb_ctrl properly
> > > > + * for the enablement, so just write the ctrl_reg here.
> > > > + */
> > > > + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(ldb_bridge_enable_helper);
> > > > +
> > > > +void ldb_bridge_disable_helper(struct drm_bridge *bridge)
> > > > +{
> > > > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > > > + struct ldb *ldb = ldb_ch->ldb;
> > > > + bool is_split = ldb_channel_is_split_link(ldb_ch);
> > > > +
> > > > + if (ldb_ch->chno == 0 || is_split)
> > > > + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
> > > > + if (ldb_ch->chno == 1 || is_split)
> > > > + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
> > > > +
> > > > + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(ldb_bridge_disable_helper);
> > > > +
> > > > +int ldb_bridge_attach_helper(struct drm_bridge *bridge,
> > > > + enum drm_bridge_attach_flags flags)
> > > > +{
> > > > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > > > + struct ldb *ldb = ldb_ch->ldb;
> > > > +
> > > > + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
> > > > + DRM_DEV_ERROR(ldb->dev,
> > > > + "do not support creating a drm_connector\n");
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + if (!bridge->encoder) {
> > > > + DRM_DEV_ERROR(ldb->dev, "missing encoder\n");
> > > > + return -ENODEV;
> > > > + }
> > > > +
> > > > + return drm_bridge_attach(bridge->encoder,
> > > > + ldb_ch->next_bridge, bridge,
> > > > + DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(ldb_bridge_attach_helper);
> > > > +
> > > > +int ldb_init_helper(struct ldb *ldb)
> > > > +{
> > > > + struct device *dev = ldb->dev;
> > > > + struct device_node *np = dev->of_node;
> > > > + struct device_node *child;
> > > > + int ret;
> > > > + u32 i;
> > > > +
> > > > + ldb->regmap = syscon_node_to_regmap(np->parent);
> > > > + if (IS_ERR(ldb->regmap)) {
> > > > + ret = PTR_ERR(ldb->regmap);
> > > > + if (ret != -EPROBE_DEFER)
> > > > + DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret);
> > > > + return ret;
> > > > + }
> > > > +
> > > > + for_each_available_child_of_node(np, child) {
> > > > + struct ldb_channel *ldb_ch;
> > > > +
> > > > + ret = of_property_read_u32(child, "reg", &i);
> > > > + if (ret || i > MAX_LDB_CHAN_NUM - 1) {
> > > > + ret = -EINVAL;
> > > > + DRM_DEV_ERROR(dev,
> > > > + "invalid channel node address: %u\n", i);
> > > > + of_node_put(child);
> > > > + return ret;
> > > > + }
> > > > +
> > > > + ldb_ch = ldb->channel[i];
> > > > + ldb_ch->ldb = ldb;
> > > > + ldb_ch->chno = i;
> > > > + ldb_ch->is_available = true;
> > > > + ldb_ch->np = child;
> > > > +
> > > > + ldb->available_ch_cnt++;
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(ldb_init_helper);
> > > > +
> > > > +int ldb_find_next_bridge_helper(struct ldb *ldb)
> > > > +{
> > > > + struct device *dev = ldb->dev;
> > > > + struct ldb_channel *ldb_ch;
> > > > + int ret, i;
> > > > +
> > > > + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
> > > > + ldb_ch = ldb->channel[i];
> > > > +
> > > > + if (!ldb_ch->is_available)
> > > > + continue;
> > > > +
> > > > + ret = drm_of_find_panel_or_bridge(ldb_ch->np, 1, 0,
> > > > + &ldb_ch->panel,
> > > > + &ldb_ch->next_bridge);
> > > > + if (ret) {
> > > > + if (ret != -EPROBE_DEFER)
> > > > + DRM_DEV_ERROR(dev,
> > > > + "failed to find panel or bridge: %d\n",
> > > > + ret);
> > > > + return ret;
> > > > + }
> > > > +
> > > > + if (ldb_ch->panel) {
> > > > + ldb_ch->next_bridge = devm_drm_panel_bridge_add(dev,
> > > > + ldb_ch->panel);
> > > > + if (IS_ERR(ldb_ch->next_bridge)) {
> > > > + ret = PTR_ERR(ldb_ch->next_bridge);
> > > > + DRM_DEV_ERROR(dev,
> > > > + "failed to add panel bridge: %d\n",
> > > > + ret);
> > > > + return ret;
> > > > + }
> > > > + }
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(ldb_find_next_bridge_helper);
> > > > +
> > > > +void ldb_add_bridge_helper(struct ldb *ldb,
> > > > + const struct drm_bridge_funcs *bridge_funcs)
> > > > +{
> > > > + struct ldb_channel *ldb_ch;
> > > > + int i;
> > > > +
> > > > + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
> > > > + ldb_ch = ldb->channel[i];
> > > > +
> > > > + if (!ldb_ch->is_available)
> > > > + continue;
> > > > +
> > > > + ldb_ch->bridge.driver_private = ldb_ch;
> > > > + ldb_ch->bridge.funcs = bridge_funcs;
> > > > + ldb_ch->bridge.of_node = ldb_ch->np;
> > > > +
> > > > + drm_bridge_add(&ldb_ch->bridge);
> > > > + }
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(ldb_add_bridge_helper);
> > > > +
> > > > +void ldb_remove_bridge_helper(struct ldb *ldb)
> > > > +{
> > > > + struct ldb_channel *ldb_ch;
> > > > + int i;
> > > > +
> > > > + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
> > > > + ldb_ch = ldb->channel[i];
> > > > +
> > > > + if (!ldb_ch->is_available)
> > > > + continue;
> > > > +
> > > > + drm_bridge_remove(&ldb_ch->bridge);
> > > > + }
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(ldb_remove_bridge_helper);
> > > > +
> > > > +MODULE_DESCRIPTION("Freescale i.MX LVDS Display Bridge driver helper");
> > > > +MODULE_AUTHOR("Liu Ying <[email protected]>");
> > > > +MODULE_LICENSE("GPL v2");
> > > > +MODULE_ALIAS("platform:imx-ldb-helper");
> > >
> > > I'm not entirely sure why this set of helper functions should be a
> > > module. It's not a driver, but rather a toolbox for the LDB driver,
> > > which is fine, but there is no situation I can see where this module
> > > would be unloaded and the LDB driver would be loaded.
> >
> > I can see drivers/gpu/drm/drm_mipi_dbi.c is also a module and
> > essentially provides helpers to MIPI DBI drivers, but it is not a
> > driver. I don't see this imx-ldb-helper can be anything else other
> > than a module.
> >
> > Or, do you mean that imx-ldb-helper should be only built-in?
>
> My thinking was that it should just be linked together with the rest
> of the imx8qxp-ldb driver. But this ties in to my next comment.

This patch set contains _two_ modules which use the imx-ldb-helper,
i.e., the imx8qxp-ldb driver(patch 12/14) and the imx8qm-ldb
driver(patch 13/14). It looks that we cannot link the imx-ldb-helper
with them respectively. So, I think keeping imx-ldb-helper as a module
is the only option.

>
> > > > diff --git a/include/drm/bridge/imx_ldb_helper.h b/include/drm/bridge/imx_ldb_helper.h
> > > > new file mode 100644
> > > > index 00000000..2a7ba97
> > > > --- /dev/null
> > > > +++ b/include/drm/bridge/imx_ldb_helper.h
> > >
> > > This header is specific to this driver, and I would expect it to not
> > > be useful to other drivers. Additionally the filename has a different
> > > format than the .c file it corresponds to. I would change the name and
> > > path to "drivers/gpu/drm/bridge/imx/imx-ldb-helper.h".
> >
> > The i.MX53/6qdl LDB driver(drivers/gpu/drm/imx/imx-ldb.c) can
> > potentially use this header, but it's a DRM encoder driver.
> > So, maybe, it's a good idea to move this header to the 'drivers' folder
> > and rename it to 'imx-ldb-helper.h' ofc. If no objections, I'll do as
> > what you're suggesting here in the next version.
>
> Ah I see. If ldb-helper is indeed used by two drivers, making it a
> module seems reasonable.

Yes, for now, two drivers(imx8qxp-ldb and imx8qm-ldb) use
imx-ldb-helper.

>
> I think we have two options then.
>
> #1 Make imx-ldb-helper an object that is just linked with the
> imx8qxp-ldb driver.

I don't think #1 is a valid option, as we cannot link imx-ldb-helper
object with imx8qxp-ldb driver and imx8qm-ldb driver respectively.

>
> #2 Keep imx-ldb-helper as a module, and implement support for using it
> in the imx-ldb driver. Ideally I'd like to see the imx-ldb-helper
> module patch in the same series as as imx53/6qdl switching to using
> the module. These things have a tendency of not happening if not done
> right away :)

As I mentioned before, the i.MX53/6qdl LDB driver(imx-ldb) is a DRM
encoder driver. It doesn't look straight-forward to include a header
for bridge drivers there.

An alternative is to first convert imx-ldb to be a pure bridge
driver(called imx53-ldb.c, perhaps) and to put it in
drivers/gpu/drm/bridge/imx folder. But, it's not an easy task, because
the imx-drm for i.MX51/53/6dql IPU display controller needs to create
DRM encoders & connectors instead, and the other relevant encoder
drivers (imx-tve, parallel-display and dw_hdmi-imx) needs to be
converted to bridge drivers as well. This is not what this patch set
can cover, IMHO. Perhaps, it will be done later on.

In all, it looks ok to keep imx-ldb-helper as a module and move the
header(imx-ldb-helper.h) to the 'drivers' folder. Agree?

Regards,
Liu Ying

>
>
> > Regards,
> > Liu Ying
> >
> > > > @@ -0,0 +1,98 @@
> > > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > > +
> > > > +/*
> > > > + * Copyright 2019,2020 NXP
> > > > + */
> > > > +
> > > > +#ifndef __FSL_IMX_LDB__
> > > > +#define __FSL_IMX_LDB__
> > > > +
> > > > +#include <linux/device.h>
> > > > +#include <linux/kernel.h>
> > > > +#include <linux/of.h>
> > > > +#include <linux/regmap.h>
> > > > +
> > > > +#include <drm/drm_atomic.h>
> > > > +#include <drm/drm_bridge.h>
> > > > +#include <drm/drm_device.h>
> > > > +#include <drm/drm_encoder.h>
> > > > +#include <drm/drm_modeset_helper_vtables.h>
> > > > +#include <drm/drm_panel.h>
> > > > +
> > > > +#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
> > > > +#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
> > > > +#define LDB_CH0_MODE_EN_MASK (3 << 0)
> > > > +#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
> > > > +#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
> > > > +#define LDB_CH1_MODE_EN_MASK (3 << 2)
> > > > +#define LDB_SPLIT_MODE_EN (1 << 4)
> > > > +#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
> > > > +#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
> > > > +#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
> > > > +#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
> > > > +#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
> > > > +#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
> > > > +
> > > > +#define MAX_LDB_CHAN_NUM 2
> > > > +
> > > > +enum ldb_channel_link_type {
> > > > + LDB_CH_SINGLE_LINK,
> > > > + LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS,
> > > > + LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS,
> > > > +};
> > > > +
> > > > +struct ldb;
> > > > +
> > > > +struct ldb_channel {
> > > > + struct ldb *ldb;
> > > > + struct drm_bridge bridge;
> > > > + struct drm_panel *panel;
> > > > + struct drm_bridge *next_bridge;
> > > > + struct device_node *np;
> > > > + u32 chno;
> > > > + bool is_available;
> > > > + u32 in_bus_format;
> > > > + u32 out_bus_format;
> > > > + enum ldb_channel_link_type link_type;
> > > > +};
> > > > +
> > > > +struct ldb {
> > > > + struct regmap *regmap;
> > > > + struct device *dev;
> > > > + struct ldb_channel *channel[MAX_LDB_CHAN_NUM];
> > > > + unsigned int ctrl_reg;
> > > > + u32 ldb_ctrl;
> > > > + unsigned int available_ch_cnt;
> > > > +};
> > > > +
> > > > +#define bridge_to_ldb_ch(b) container_of(b, struct ldb_channel, bridge)
> > > > +
> > > > +bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch);
> > > > +bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch);
> > > > +
> > > > +int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
> > > > + struct drm_bridge_state *bridge_state,
> > > > + struct drm_crtc_state *crtc_state,
> > > > + struct drm_connector_state *conn_state);
> > > > +
> > > > +void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
> > > > + const struct drm_display_mode *mode,
> > > > + const struct drm_display_mode *adjusted_mode);
> > > > +
> > > > +void ldb_bridge_enable_helper(struct drm_bridge *bridge);
> > > > +
> > > > +void ldb_bridge_disable_helper(struct drm_bridge *bridge);
> > > > +
> > > > +int ldb_bridge_attach_helper(struct drm_bridge *bridge,
> > > > + enum drm_bridge_attach_flags flags);
> > > > +
> > > > +int ldb_init_helper(struct ldb *ldb);
> > > > +
> > > > +int ldb_find_next_bridge_helper(struct ldb *ldb);
> > > > +
> > > > +void ldb_add_bridge_helper(struct ldb *ldb,
> > > > + const struct drm_bridge_funcs *bridge_funcs);
> > > > +
> > > > +void ldb_remove_bridge_helper(struct ldb *ldb);
> > > > +
> > > > +#endif /* __FSL_IMX_LDB__ */
> > > > --
> > > > 2.7.4
> > > >

2021-03-05 22:44:51

by Rob Herring (Arm)

[permalink] [raw]
Subject: Re: [PATCH v4 08/14] dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding

On Thu, Feb 18, 2021 at 11:41:49AM +0800, Liu Ying wrote:
> This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).
>
> Signed-off-by: Liu Ying <[email protected]>
> ---
> v3->v4:
> * Add 'fsl,sc-resource' property. (Rob)
>
> v2->v3:
> * Drop 'fsl,syscon' property. (Rob)
> * Mention the CSR module controls PXL2DPI.
>
> v1->v2:
> * Use graph schema. (Laurent)
>
> .../display/bridge/fsl,imx8qxp-pxl2dpi.yaml | 108 +++++++++++++++++++++
> 1 file changed, 108 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
> new file mode 100644
> index 00000000..e4e77fa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
> +
> +maintainers:
> + - Liu Ying <[email protected]>
> +
> +description: |
> + The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
> + interfaces the pixel link 36-bit data output and the DSI controller’s
> + MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
> + used in LVDS mode, to remap the pixel color codings between those modules.
> + This module is purely combinatorial.
> +
> + The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
> + The CSR module, as a system controller, contains the PXL2DPI's configuration
> + register.

So this node should be a child of the CSR. Ideally, this schema is also
referenced from the CSR's schema (and if that doesn't exist, it should
be there first).

> +
> +properties:
> + compatible:
> + const: fsl,imx8qxp-pxl2dpi
> +
> + fsl,sc-resource:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: The SCU resource ID associated with this PXL2DPI instance.
> +
> + power-domains:
> + maxItems: 1
> +
> + fsl,companion-pxl2dpi:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: |
> + A phandle which points to companion PXL2DPI which is used by downstream
> + LVDS Display Bridge(LDB) in split mode.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: The PXL2DPI input port node from pixel link.
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: The PXL2DPI output port node to downstream bridge.
> +
> + required:
> + - port@0
> + - port@1
> +
> +required:
> + - compatible
> + - fsl,sc-resource
> + - power-domains
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/firmware/imx/rsrc.h>
> + pxl2dpi {
> + compatible = "fsl,imx8qxp-pxl2dpi";
> + fsl,sc-resource = <IMX_SC_R_MIPI_0>;
> + power-domains = <&pd IMX_SC_R_MIPI_0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> +
> + mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>;
> + };
> +
> + mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;
> + };
> + };
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
> + };
> +
> + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
> + };
> + };
> + };
> + };
> --
> 2.7.4
>

2021-03-08 10:19:15

by Liu Ying

[permalink] [raw]
Subject: Re: [PATCH v4 08/14] dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding

Hi Rob,

On Fri, 2021-03-05 at 16:42 -0600, Rob Herring wrote:
> On Thu, Feb 18, 2021 at 11:41:49AM +0800, Liu Ying wrote:
> > This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).
> >
> > Signed-off-by: Liu Ying <[email protected]>
> > ---
> > v3->v4:
> > * Add 'fsl,sc-resource' property. (Rob)
> >
> > v2->v3:
> > * Drop 'fsl,syscon' property. (Rob)
> > * Mention the CSR module controls PXL2DPI.
> >
> > v1->v2:
> > * Use graph schema. (Laurent)
> >
> > .../display/bridge/fsl,imx8qxp-pxl2dpi.yaml | 108 +++++++++++++++++++++
> > 1 file changed, 108 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
> > new file mode 100644
> > index 00000000..e4e77fa
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
> > @@ -0,0 +1,108 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fdisplay%2Fbridge%2Ffsl%2Cimx8qxp-pxl2dpi.yaml%23&amp;data=04%7C01%7Cvictor.liu%40nxp.com%7Ca37ec67ba3274bcea5c408d8e027f69b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637505809544037562%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=UN2IQps7q5vK6uNG8fQTn1Klgn0cVyuYnUeqxrjCWHo%3D&amp;reserved=0
> > +$schema: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cvictor.liu%40nxp.com%7Ca37ec67ba3274bcea5c408d8e027f69b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637505809544037562%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=cvJVL3Fp1hwbjj1jO1YAozKdZATt5DJ78E7vGT%2F25Oc%3D&amp;reserved=0
> > +
> > +title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
> > +
> > +maintainers:
> > + - Liu Ying <[email protected]>
> > +
> > +description: |
> > + The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
> > + interfaces the pixel link 36-bit data output and the DSI controller’s
> > + MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
> > + used in LVDS mode, to remap the pixel color codings between those modules.
> > + This module is purely combinatorial.
> > +
> > + The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
> > + The CSR module, as a system controller, contains the PXL2DPI's configuration
> > + register.
>
> So this node should be a child of the CSR. Ideally, this schema is also
> referenced from the CSR's schema (and if that doesn't exist, it should
> be there first).

I can add a patch to introduce a schema for the CSR in this series,
just prior to this patch. Do you think if that will be fine?

Thanks,
Liu Ying

>
> > +
> > +properties:
> > + compatible:
> > + const: fsl,imx8qxp-pxl2dpi
> > +
> > + fsl,sc-resource:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: The SCU resource ID associated with this PXL2DPI instance.
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + fsl,companion-pxl2dpi:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: |
> > + A phandle which points to companion PXL2DPI which is used by downstream
> > + LVDS Display Bridge(LDB) in split mode.
> > +
> > + ports:
> > + $ref: /schemas/graph.yaml#/properties/ports
> > +
> > + properties:
> > + port@0:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description: The PXL2DPI input port node from pixel link.
> > +
> > + port@1:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description: The PXL2DPI output port node to downstream bridge.
> > +
> > + required:
> > + - port@0
> > + - port@1
> > +
> > +required:
> > + - compatible
> > + - fsl,sc-resource
> > + - power-domains
> > + - ports
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/firmware/imx/rsrc.h>
> > + pxl2dpi {
> > + compatible = "fsl,imx8qxp-pxl2dpi";
> > + fsl,sc-resource = <IMX_SC_R_MIPI_0>;
> > + power-domains = <&pd IMX_SC_R_MIPI_0>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0>;
> > +
> > + mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 {
> > + reg = <0>;
> > + remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>;
> > + };
> > +
> > + mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 {
> > + reg = <1>;
> > + remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;
> > + };
> > + };
> > +
> > + port@1 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <1>;
> > +
> > + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
> > + reg = <0>;
> > + remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
> > + };
> > +
> > + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
> > + reg = <1>;
> > + remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
> > + };
> > + };
> > + };
> > + };
> > --
> > 2.7.4
> >

2021-03-08 10:23:08

by Liu Ying

[permalink] [raw]
Subject: Re: [PATCH v4 10/14] drm/bridge: imx: Add LDB driver helper support

Hi Robert,

On Thu, 2021-03-04 at 11:27 +0800, Liu Ying wrote:
> Hi Robert,
>
> On Wed, 2021-03-03 at 16:34 +0100, Robert Foss wrote:
> > On Wed, 3 Mar 2021 at 08:23, Liu Ying <[email protected]> wrote:
> > > Hi Robert,
> > >
> > > On Tue, 2021-03-02 at 15:22 +0100, Robert Foss wrote:
> > > > Hey Liu,
> > > >
> > > > Thanks for submitting this patch.
> > >
> > > Thanks for reviewing this patch.
> > >
> > > > On Thu, 18 Feb 2021 at 04:59, Liu Ying <[email protected]> wrote:
> > > > > This patch adds a helper to support LDB drm bridge drivers for
> > > > > i.MX SoCs. Helper functions exported from this driver should
> > > > > implement common logics for all LDB modules embedded in i.MX SoCs.
> > > > >
> > > > > Signed-off-by: Liu Ying <[email protected]>
> > > > > ---
> > > > > v3->v4:
> > > > > * No change.
> > > > >
> > > > > v2->v3:
> > > > > * Call syscon_node_to_regmap() to get regmap instead of
> > > > > syscon_regmap_lookup_by_phandle().
> > > > >
> > > > > v1->v2:
> > > > > * No change.
> > > > >
> > > > > drivers/gpu/drm/bridge/imx/Kconfig | 8 +
> > > > > drivers/gpu/drm/bridge/imx/Makefile | 1 +
> > > > > drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 248 ++++++++++++++++++++++++++++
> > > > > include/drm/bridge/imx_ldb_helper.h | 98 +++++++++++
> > > > > 4 files changed, 355 insertions(+)
> > > > > create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
> > > > > create mode 100644 include/drm/bridge/imx_ldb_helper.h
> > > > >
> > > > > diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
> > > > > index 1ea1ce7..23e24fd 100644
> > > > > --- a/drivers/gpu/drm/bridge/imx/Kconfig
> > > > > +++ b/drivers/gpu/drm/bridge/imx/Kconfig
> > > > > @@ -1,3 +1,11 @@
> > > > > +config DRM_IMX_LVDS_BRIDGE_HELPER
> > > > > + tristate "Freescale i.MX LVDS display bridge helper"
> > > > > + depends on OF
> > > > > + select DRM_PANEL_BRIDGE
> > > > > + help
> > > > > + Helper to support Freescale i.MX LVDS Display Bridge(LDB).
> > > > > + This bridge is embedded in a SoC.
> > > > > +
> > > > > config DRM_IMX8QXP_PIXEL_COMBINER
> > > > > tristate "Freescale i.MX8QM/QXP pixel combiner"
> > > > > depends on OF
> > > > > diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
> > > > > index e74dd64..902b703 100644
> > > > > --- a/drivers/gpu/drm/bridge/imx/Makefile
> > > > > +++ b/drivers/gpu/drm/bridge/imx/Makefile
> > > > > @@ -1,3 +1,4 @@
> > > > > +obj-$(CONFIG_DRM_IMX_LVDS_BRIDGE_HELPER) += imx-ldb-helper.o
> > > > > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
> > > > > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
> > > > > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
> > > > > diff --git a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
> > > > > new file mode 100644
> > > > > index 00000000..94d7f9e
> > > > > --- /dev/null
> > > > > +++ b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
> > > > > @@ -0,0 +1,248 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > +/*
> > > > > + * Copyright (C) 2012 Sascha Hauer, Pengutronix
> > > > > + * Copyright 2019,2020 NXP
> > > > > + */
> > > > > +
> > > > > +#include <linux/mfd/syscon.h>
> > > > > +#include <linux/module.h>
> > > > > +#include <linux/of.h>
> > > > > +#include <linux/regmap.h>
> > > > > +
> > > > > +#include <drm/bridge/imx_ldb_helper.h>
> > > > > +#include <drm/drm_of.h>
> > > > > +#include <drm/drm_panel.h>
> > > > > +#include <drm/drm_print.h>
> > > > > +
> > > > > +bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch)
> > > > > +{
> > > > > + return ldb_ch->link_type == LDB_CH_SINGLE_LINK;
> > > > > +}
> > > > > +EXPORT_SYMBOL_GPL(ldb_channel_is_single_link);
> > > > > +
> > > > > +bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch)
> > > > > +{
> > > > > + return ldb_ch->link_type == LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS ||
> > > > > + ldb_ch->link_type == LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS;
> > > > > +}
> > > > > +EXPORT_SYMBOL_GPL(ldb_channel_is_split_link);
> > > > > +
> > > > > +int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
> > > > > + struct drm_bridge_state *bridge_state,
> > > > > + struct drm_crtc_state *crtc_state,
> > > > > + struct drm_connector_state *conn_state)
> > > > > +{
> > > > > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > > > > +
> > > > > + ldb_ch->in_bus_format = bridge_state->input_bus_cfg.format;
> > > > > + ldb_ch->out_bus_format = bridge_state->output_bus_cfg.format;
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +EXPORT_SYMBOL_GPL(ldb_bridge_atomic_check_helper);
> > > > > +
> > > > > +void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
> > > > > + const struct drm_display_mode *mode,
> > > > > + const struct drm_display_mode *adjusted_mode)
> > > > > +{
> > > > > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > > > > + struct ldb *ldb = ldb_ch->ldb;
> > > > > + bool is_split = ldb_channel_is_split_link(ldb_ch);
> > > > > +
> > > > > + if (is_split)
> > > > > + ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
> > > > > +
> > > > > + switch (ldb_ch->out_bus_format) {
> > > > > + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
> > > > > + break;
> > > > > + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
> > > > > + if (ldb_ch->chno == 0 || is_split)
> > > > > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
> > > > > + if (ldb_ch->chno == 1 || is_split)
> > > > > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
> > > > > + break;
> > > > > + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
> > > > > + if (ldb_ch->chno == 0 || is_split)
> > > > > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
> > > > > + LDB_BIT_MAP_CH0_JEIDA;
> > > > > + if (ldb_ch->chno == 1 || is_split)
> > > > > + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
> > > > > + LDB_BIT_MAP_CH1_JEIDA;
> > > > > + break;
> > > > > + }
> > > > > +}
> > > > > +EXPORT_SYMBOL_GPL(ldb_bridge_mode_set_helper);
> > > > > +
> > > > > +void ldb_bridge_enable_helper(struct drm_bridge *bridge)
> > > > > +{
> > > > > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > > > > + struct ldb *ldb = ldb_ch->ldb;
> > > > > +
> > > > > + /*
> > > > > + * Platform specific bridge drivers should set ldb_ctrl properly
> > > > > + * for the enablement, so just write the ctrl_reg here.
> > > > > + */
> > > > > + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
> > > > > +}
> > > > > +EXPORT_SYMBOL_GPL(ldb_bridge_enable_helper);
> > > > > +
> > > > > +void ldb_bridge_disable_helper(struct drm_bridge *bridge)
> > > > > +{
> > > > > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > > > > + struct ldb *ldb = ldb_ch->ldb;
> > > > > + bool is_split = ldb_channel_is_split_link(ldb_ch);
> > > > > +
> > > > > + if (ldb_ch->chno == 0 || is_split)
> > > > > + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
> > > > > + if (ldb_ch->chno == 1 || is_split)
> > > > > + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
> > > > > +
> > > > > + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl);
> > > > > +}
> > > > > +EXPORT_SYMBOL_GPL(ldb_bridge_disable_helper);
> > > > > +
> > > > > +int ldb_bridge_attach_helper(struct drm_bridge *bridge,
> > > > > + enum drm_bridge_attach_flags flags)
> > > > > +{
> > > > > + struct ldb_channel *ldb_ch = bridge->driver_private;
> > > > > + struct ldb *ldb = ldb_ch->ldb;
> > > > > +
> > > > > + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
> > > > > + DRM_DEV_ERROR(ldb->dev,
> > > > > + "do not support creating a drm_connector\n");
> > > > > + return -EINVAL;
> > > > > + }
> > > > > +
> > > > > + if (!bridge->encoder) {
> > > > > + DRM_DEV_ERROR(ldb->dev, "missing encoder\n");
> > > > > + return -ENODEV;
> > > > > + }
> > > > > +
> > > > > + return drm_bridge_attach(bridge->encoder,
> > > > > + ldb_ch->next_bridge, bridge,
> > > > > + DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> > > > > +}
> > > > > +EXPORT_SYMBOL_GPL(ldb_bridge_attach_helper);
> > > > > +
> > > > > +int ldb_init_helper(struct ldb *ldb)
> > > > > +{
> > > > > + struct device *dev = ldb->dev;
> > > > > + struct device_node *np = dev->of_node;
> > > > > + struct device_node *child;
> > > > > + int ret;
> > > > > + u32 i;
> > > > > +
> > > > > + ldb->regmap = syscon_node_to_regmap(np->parent);
> > > > > + if (IS_ERR(ldb->regmap)) {
> > > > > + ret = PTR_ERR(ldb->regmap);
> > > > > + if (ret != -EPROBE_DEFER)
> > > > > + DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret);
> > > > > + return ret;
> > > > > + }
> > > > > +
> > > > > + for_each_available_child_of_node(np, child) {
> > > > > + struct ldb_channel *ldb_ch;
> > > > > +
> > > > > + ret = of_property_read_u32(child, "reg", &i);
> > > > > + if (ret || i > MAX_LDB_CHAN_NUM - 1) {
> > > > > + ret = -EINVAL;
> > > > > + DRM_DEV_ERROR(dev,
> > > > > + "invalid channel node address: %u\n", i);
> > > > > + of_node_put(child);
> > > > > + return ret;
> > > > > + }
> > > > > +
> > > > > + ldb_ch = ldb->channel[i];
> > > > > + ldb_ch->ldb = ldb;
> > > > > + ldb_ch->chno = i;
> > > > > + ldb_ch->is_available = true;
> > > > > + ldb_ch->np = child;
> > > > > +
> > > > > + ldb->available_ch_cnt++;
> > > > > + }
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +EXPORT_SYMBOL_GPL(ldb_init_helper);
> > > > > +
> > > > > +int ldb_find_next_bridge_helper(struct ldb *ldb)
> > > > > +{
> > > > > + struct device *dev = ldb->dev;
> > > > > + struct ldb_channel *ldb_ch;
> > > > > + int ret, i;
> > > > > +
> > > > > + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
> > > > > + ldb_ch = ldb->channel[i];
> > > > > +
> > > > > + if (!ldb_ch->is_available)
> > > > > + continue;
> > > > > +
> > > > > + ret = drm_of_find_panel_or_bridge(ldb_ch->np, 1, 0,
> > > > > + &ldb_ch->panel,
> > > > > + &ldb_ch->next_bridge);
> > > > > + if (ret) {
> > > > > + if (ret != -EPROBE_DEFER)
> > > > > + DRM_DEV_ERROR(dev,
> > > > > + "failed to find panel or bridge: %d\n",
> > > > > + ret);
> > > > > + return ret;
> > > > > + }
> > > > > +
> > > > > + if (ldb_ch->panel) {
> > > > > + ldb_ch->next_bridge = devm_drm_panel_bridge_add(dev,
> > > > > + ldb_ch->panel);
> > > > > + if (IS_ERR(ldb_ch->next_bridge)) {
> > > > > + ret = PTR_ERR(ldb_ch->next_bridge);
> > > > > + DRM_DEV_ERROR(dev,
> > > > > + "failed to add panel bridge: %d\n",
> > > > > + ret);
> > > > > + return ret;
> > > > > + }
> > > > > + }
> > > > > + }
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +EXPORT_SYMBOL_GPL(ldb_find_next_bridge_helper);
> > > > > +
> > > > > +void ldb_add_bridge_helper(struct ldb *ldb,
> > > > > + const struct drm_bridge_funcs *bridge_funcs)
> > > > > +{
> > > > > + struct ldb_channel *ldb_ch;
> > > > > + int i;
> > > > > +
> > > > > + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
> > > > > + ldb_ch = ldb->channel[i];
> > > > > +
> > > > > + if (!ldb_ch->is_available)
> > > > > + continue;
> > > > > +
> > > > > + ldb_ch->bridge.driver_private = ldb_ch;
> > > > > + ldb_ch->bridge.funcs = bridge_funcs;
> > > > > + ldb_ch->bridge.of_node = ldb_ch->np;
> > > > > +
> > > > > + drm_bridge_add(&ldb_ch->bridge);
> > > > > + }
> > > > > +}
> > > > > +EXPORT_SYMBOL_GPL(ldb_add_bridge_helper);
> > > > > +
> > > > > +void ldb_remove_bridge_helper(struct ldb *ldb)
> > > > > +{
> > > > > + struct ldb_channel *ldb_ch;
> > > > > + int i;
> > > > > +
> > > > > + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
> > > > > + ldb_ch = ldb->channel[i];
> > > > > +
> > > > > + if (!ldb_ch->is_available)
> > > > > + continue;
> > > > > +
> > > > > + drm_bridge_remove(&ldb_ch->bridge);
> > > > > + }
> > > > > +}
> > > > > +EXPORT_SYMBOL_GPL(ldb_remove_bridge_helper);
> > > > > +
> > > > > +MODULE_DESCRIPTION("Freescale i.MX LVDS Display Bridge driver helper");
> > > > > +MODULE_AUTHOR("Liu Ying <[email protected]>");
> > > > > +MODULE_LICENSE("GPL v2");
> > > > > +MODULE_ALIAS("platform:imx-ldb-helper");
> > > >
> > > > I'm not entirely sure why this set of helper functions should be a
> > > > module. It's not a driver, but rather a toolbox for the LDB driver,
> > > > which is fine, but there is no situation I can see where this module
> > > > would be unloaded and the LDB driver would be loaded.
> > >
> > > I can see drivers/gpu/drm/drm_mipi_dbi.c is also a module and
> > > essentially provides helpers to MIPI DBI drivers, but it is not a
> > > driver. I don't see this imx-ldb-helper can be anything else other
> > > than a module.
> > >
> > > Or, do you mean that imx-ldb-helper should be only built-in?
> >
> > My thinking was that it should just be linked together with the rest
> > of the imx8qxp-ldb driver. But this ties in to my next comment.
>
> This patch set contains _two_ modules which use the imx-ldb-helper,
> i.e., the imx8qxp-ldb driver(patch 12/14) and the imx8qm-ldb
> driver(patch 13/14). It looks that we cannot link the imx-ldb-helper
> with them respectively. So, I think keeping imx-ldb-helper as a module
> is the only option.

I need to change my saying here. I think we can link the
imx-ldb-helper with those two drivers respectively.
So, I assume imx-ldb-helper won't be a module, then.

And, I still don't think this series should touch the i.MX53/6qdl LDB
driver(imx-ldb).

If no strong opinions, I would try the updated option#1 for the next
version:

#1(updated) Make imx-ldb-helper an object that is just linked with the
imx8qxp-ldb driver and the imx8qm-ldb driver.

Regards,
Liu Ying

>
> > > > > diff --git a/include/drm/bridge/imx_ldb_helper.h b/include/drm/bridge/imx_ldb_helper.h
> > > > > new file mode 100644
> > > > > index 00000000..2a7ba97
> > > > > --- /dev/null
> > > > > +++ b/include/drm/bridge/imx_ldb_helper.h
> > > >
> > > > This header is specific to this driver, and I would expect it to not
> > > > be useful to other drivers. Additionally the filename has a different
> > > > format than the .c file it corresponds to. I would change the name and
> > > > path to "drivers/gpu/drm/bridge/imx/imx-ldb-helper.h".
> > >
> > > The i.MX53/6qdl LDB driver(drivers/gpu/drm/imx/imx-ldb.c) can
> > > potentially use this header, but it's a DRM encoder driver.
> > > So, maybe, it's a good idea to move this header to the 'drivers' folder
> > > and rename it to 'imx-ldb-helper.h' ofc. If no objections, I'll do as
> > > what you're suggesting here in the next version.
> >
> > Ah I see. If ldb-helper is indeed used by two drivers, making it a
> > module seems reasonable.
>
> Yes, for now, two drivers(imx8qxp-ldb and imx8qm-ldb) use
> imx-ldb-helper.
>
> > I think we have two options then.
> >
> > #1 Make imx-ldb-helper an object that is just linked with the
> > imx8qxp-ldb driver.
>
> I don't think #1 is a valid option, as we cannot link imx-ldb-helper
> object with imx8qxp-ldb driver and imx8qm-ldb driver respectively.
>
> > #2 Keep imx-ldb-helper as a module, and implement support for using it
> > in the imx-ldb driver. Ideally I'd like to see the imx-ldb-helper
> > module patch in the same series as as imx53/6qdl switching to using
> > the module. These things have a tendency of not happening if not done
> > right away :)
>
> As I mentioned before, the i.MX53/6qdl LDB driver(imx-ldb) is a DRM
> encoder driver. It doesn't look straight-forward to include a header
> for bridge drivers there.
>
> An alternative is to first convert imx-ldb to be a pure bridge
> driver(called imx53-ldb.c, perhaps) and to put it in
> drivers/gpu/drm/bridge/imx folder. But, it's not an easy task, because
> the imx-drm for i.MX51/53/6dql IPU display controller needs to create
> DRM encoders & connectors instead, and the other relevant encoder
> drivers (imx-tve, parallel-display and dw_hdmi-imx) needs to be
> converted to bridge drivers as well. This is not what this patch set
> can cover, IMHO. Perhaps, it will be done later on.
>
> In all, it looks ok to keep imx-ldb-helper as a module and move the
> header(imx-ldb-helper.h) to the 'drivers' folder. Agree?
>
> Regards,
> Liu Ying
>
> >
> > > Regards,
> > > Liu Ying
> > >
> > > > > @@ -0,0 +1,98 @@
> > > > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > > > +
> > > > > +/*
> > > > > + * Copyright 2019,2020 NXP
> > > > > + */
> > > > > +
> > > > > +#ifndef __FSL_IMX_LDB__
> > > > > +#define __FSL_IMX_LDB__
> > > > > +
> > > > > +#include <linux/device.h>
> > > > > +#include <linux/kernel.h>
> > > > > +#include <linux/of.h>
> > > > > +#include <linux/regmap.h>
> > > > > +
> > > > > +#include <drm/drm_atomic.h>
> > > > > +#include <drm/drm_bridge.h>
> > > > > +#include <drm/drm_device.h>
> > > > > +#include <drm/drm_encoder.h>
> > > > > +#include <drm/drm_modeset_helper_vtables.h>
> > > > > +#include <drm/drm_panel.h>
> > > > > +
> > > > > +#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
> > > > > +#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
> > > > > +#define LDB_CH0_MODE_EN_MASK (3 << 0)
> > > > > +#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
> > > > > +#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
> > > > > +#define LDB_CH1_MODE_EN_MASK (3 << 2)
> > > > > +#define LDB_SPLIT_MODE_EN (1 << 4)
> > > > > +#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
> > > > > +#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
> > > > > +#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
> > > > > +#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
> > > > > +#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
> > > > > +#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
> > > > > +
> > > > > +#define MAX_LDB_CHAN_NUM 2
> > > > > +
> > > > > +enum ldb_channel_link_type {
> > > > > + LDB_CH_SINGLE_LINK,
> > > > > + LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS,
> > > > > + LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS,
> > > > > +};
> > > > > +
> > > > > +struct ldb;
> > > > > +
> > > > > +struct ldb_channel {
> > > > > + struct ldb *ldb;
> > > > > + struct drm_bridge bridge;
> > > > > + struct drm_panel *panel;
> > > > > + struct drm_bridge *next_bridge;
> > > > > + struct device_node *np;
> > > > > + u32 chno;
> > > > > + bool is_available;
> > > > > + u32 in_bus_format;
> > > > > + u32 out_bus_format;
> > > > > + enum ldb_channel_link_type link_type;
> > > > > +};
> > > > > +
> > > > > +struct ldb {
> > > > > + struct regmap *regmap;
> > > > > + struct device *dev;
> > > > > + struct ldb_channel *channel[MAX_LDB_CHAN_NUM];
> > > > > + unsigned int ctrl_reg;
> > > > > + u32 ldb_ctrl;
> > > > > + unsigned int available_ch_cnt;
> > > > > +};
> > > > > +
> > > > > +#define bridge_to_ldb_ch(b) container_of(b, struct ldb_channel, bridge)
> > > > > +
> > > > > +bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch);
> > > > > +bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch);
> > > > > +
> > > > > +int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
> > > > > + struct drm_bridge_state *bridge_state,
> > > > > + struct drm_crtc_state *crtc_state,
> > > > > + struct drm_connector_state *conn_state);
> > > > > +
> > > > > +void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
> > > > > + const struct drm_display_mode *mode,
> > > > > + const struct drm_display_mode *adjusted_mode);
> > > > > +
> > > > > +void ldb_bridge_enable_helper(struct drm_bridge *bridge);
> > > > > +
> > > > > +void ldb_bridge_disable_helper(struct drm_bridge *bridge);
> > > > > +
> > > > > +int ldb_bridge_attach_helper(struct drm_bridge *bridge,
> > > > > + enum drm_bridge_attach_flags flags);
> > > > > +
> > > > > +int ldb_init_helper(struct ldb *ldb);
> > > > > +
> > > > > +int ldb_find_next_bridge_helper(struct ldb *ldb);
> > > > > +
> > > > > +void ldb_add_bridge_helper(struct ldb *ldb,
> > > > > + const struct drm_bridge_funcs *bridge_funcs);
> > > > > +
> > > > > +void ldb_remove_bridge_helper(struct ldb *ldb);
> > > > > +
> > > > > +#endif /* __FSL_IMX_LDB__ */
> > > > > --
> > > > > 2.7.4
> > > > >