Hi,
This is the v8 series to introduce i.MX8qm/qxp Display Processing Unit(DPU)
DRM support.
DPU is comprised of a blit engine for 2D graphics, a display controller
and a command sequencer. Outside of DPU, optional prefetch engines can
fetch data from memory prior to some DPU fetchunits of blit engine and
display controller. The pre-fetchers support linear formats and Vivante
GPU tile formats.
Reference manual can be found at:
https://www.nxp.com/webapp/Download?colCode=IMX8DQXPRM
This patch set adds kernel modesetting support for the display controller part.
It supports two CRTCs per display controller, several planes, prefetch
engines and some properties of CRTC and plane. Currently, the registers of
the controller is accessed without command sequencer involved, instead just by
using CPU. DRM connectors would be created from the DPU KMS driver.
If people want to try this series with i.MX8qxp, clock patches have already
landed in 5.12-rc1, and power domain patches have already landed in 5.11-rc1.
Version2 dropped the device tree patches because we'll use new dt binding
way to support i.MX8qm/qxp clocks. It depends on the below series to do basic
conversions for the platforms which has not landed yet:
https://www.spinics.net/lists/linux-mmc/msg61965.html
I've sent the below series to add downstream bridges(embedded in i.MX8qm/qxp)
to support LVDS displays:
https://www.spinics.net/lists/arm-kernel/msg876784.html
Patch 1 ~ 3 add dt-bindings for DPU and prefetch engines.
Patch 4 is a minor improvement of a macro to suppress warning as the KMS driver
uses it.
Patch 5 introduces the DPU DRM support.
Patch 6 updates MAINTAINERS.
Welcome comments, thanks.
v7->v8:
* Rebase this series up onto the latest drm-misc-next branch, due to DRM plane
helper functions API change(atomic_check and atomic_update) from DRM atomic
core. So, dpu_plane_atomic_check() and dpu_plane_atomic_update() are updated
accordingly in patch 5/6. Also, rename plane->state variables and relevant
DPU plane state variables in those two functions to reflect they are new
states, like the patch 'drm: Rename plane->state variables in atomic update
and disable' recently landed in drm-misc-next.
* Replace drm_gem_fb_prepare_fb() with drm_gem_plane_helper_prepare_fb() in
patch 5/6, due to DRM core API change.
* Improve DPR burst length for GPU standard tile and 32bpp GPU super tile in
patch 5/6 to align with the latest version of internal HW documention.
v6->v7:
* Fix return value of dpu_get_irqs() if platform_get_irq() fails. (Laurentiu)
* Use the function array dpu_irq_handler[] to store individual DPU irq handlers.
(Laurentiu)
* Call get/put() hooks directly to get/put DPU fetchunits for DPU plane groups.
(Laurentiu)
* Shorten the names of individual DPU irq handlers by using DPU unit abbrev
names to make writing dpu_irq_handler[] easier.
* Add Rob's R-b tag back on DPU dt-binding patch as change in v6 was reviewed.
v5->v6:
* Use graph schema in the DPU dt-binding.
* Do not use macros where possible in the DPU DRM driver. (Laurentiu)
* Break dpu_plane_atomic_check() into some smaller functions. (Laurentiu)
* Address some minor comments from Laurentiu on the DPU DRM driver.
* Add dpu_crtc_err() helper marco in the DPU DRM driver to tell dmesg
which CRTC generates error.
* Drop calling dev_set_drvdata() from dpu_drm_bind/unbind() in the DPU DRM
driver as it is done in dpu_drm_probe().
* Some trivial tweaks.
v4->v5:
* Rebase up onto the latest drm-misc-next branch and remove the hook to
drm_atomic_helper_legacy_gamma_set() from patch 5/6, because it was dropped
by the newly landed commit 'drm: automatic legacy gamma support'.
* Remove a redundant blank line from dpu_plane_atomic_update() in patch 5/6.
v3->v4:
* Improve compatible properties in DPU and prefetch engines' dt bindings
by using enum instead of oneOf+const.
* Add Rob's R-b tags on dt binding patches(patch 1/6, 2/6 and 3/6).
* Add Daniel's A-b tag on patch 4/6.
v2->v3:
* Fix DPU DRM driver build warnings which are
Reported-by: kernel test robot <[email protected]>.
* Drop DPU DRM driver build dependency on IMX_SCU, as dummy SCU functions have
been added in header files by the patch 'firmware: imx: add dummy functions'
which has landed in linux-next/master branch.
* Add a missing blank line in include/drm/drm_atomic.h.
v1->v2:
* Test this patch set also with i.MX8qm LVDS displays.
* Drop the device tree patches because we'll use new dt binding way to
support i.MX8qm/qxp clocks. This depends on a not-yet-landed patch set
to do basic conversions for the platforms.
* Fix dt binding yamllint warnings.
* Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm in DPU's
dt binding documentation.
* Use new dt binding way to add clocks in the dt binding examples.
* Address several comments from Laurentiu on the DPU DRM patch.
Liu Ying (6):
dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding
dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding
dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding
drm/atomic: Avoid unused-but-set-variable warning on
for_each_old_plane_in_state
drm/imx: Introduce i.MX8qm/qxp DPU DRM
MAINTAINERS: add maintainer for i.MX8qxp DPU DRM driver
.../bindings/display/imx/fsl,imx8qxp-dprc.yaml | 87 ++
.../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 387 +++++++
.../bindings/display/imx/fsl,imx8qxp-prg.yaml | 60 ++
MAINTAINERS | 9 +
drivers/gpu/drm/imx/Kconfig | 1 +
drivers/gpu/drm/imx/Makefile | 1 +
drivers/gpu/drm/imx/dpu/Kconfig | 10 +
drivers/gpu/drm/imx/dpu/Makefile | 10 +
drivers/gpu/drm/imx/dpu/dpu-constframe.c | 171 ++++
drivers/gpu/drm/imx/dpu/dpu-core.c | 1054 ++++++++++++++++++++
drivers/gpu/drm/imx/dpu/dpu-crtc.c | 967 ++++++++++++++++++
drivers/gpu/drm/imx/dpu/dpu-crtc.h | 66 ++
drivers/gpu/drm/imx/dpu/dpu-disengcfg.c | 117 +++
drivers/gpu/drm/imx/dpu/dpu-dprc.c | 722 ++++++++++++++
drivers/gpu/drm/imx/dpu/dpu-dprc.h | 40 +
drivers/gpu/drm/imx/dpu/dpu-drv.c | 292 ++++++
drivers/gpu/drm/imx/dpu/dpu-drv.h | 28 +
drivers/gpu/drm/imx/dpu/dpu-extdst.c | 299 ++++++
drivers/gpu/drm/imx/dpu/dpu-fetchdecode.c | 294 ++++++
drivers/gpu/drm/imx/dpu/dpu-fetcheco.c | 224 +++++
drivers/gpu/drm/imx/dpu/dpu-fetchlayer.c | 154 +++
drivers/gpu/drm/imx/dpu/dpu-fetchunit.c | 609 +++++++++++
drivers/gpu/drm/imx/dpu/dpu-fetchunit.h | 191 ++++
drivers/gpu/drm/imx/dpu/dpu-fetchwarp.c | 250 +++++
drivers/gpu/drm/imx/dpu/dpu-framegen.c | 395 ++++++++
drivers/gpu/drm/imx/dpu/dpu-gammacor.c | 223 +++++
drivers/gpu/drm/imx/dpu/dpu-hscaler.c | 275 +++++
drivers/gpu/drm/imx/dpu/dpu-kms.c | 540 ++++++++++
drivers/gpu/drm/imx/dpu/dpu-kms.h | 23 +
drivers/gpu/drm/imx/dpu/dpu-layerblend.c | 348 +++++++
drivers/gpu/drm/imx/dpu/dpu-plane.c | 802 +++++++++++++++
drivers/gpu/drm/imx/dpu/dpu-plane.h | 56 ++
drivers/gpu/drm/imx/dpu/dpu-prg.c | 433 ++++++++
drivers/gpu/drm/imx/dpu/dpu-prg.h | 45 +
drivers/gpu/drm/imx/dpu/dpu-prv.h | 233 +++++
drivers/gpu/drm/imx/dpu/dpu-tcon.c | 250 +++++
drivers/gpu/drm/imx/dpu/dpu-vscaler.c | 308 ++++++
drivers/gpu/drm/imx/dpu/dpu.h | 385 +++++++
include/drm/drm_atomic.h | 5 +-
39 files changed, 10363 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
create mode 100644 drivers/gpu/drm/imx/dpu/Kconfig
create mode 100644 drivers/gpu/drm/imx/dpu/Makefile
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-constframe.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-core.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-crtc.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-crtc.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-disengcfg.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-dprc.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-dprc.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-drv.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-drv.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-extdst.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchdecode.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetcheco.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchlayer.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchunit.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchunit.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-fetchwarp.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-framegen.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-gammacor.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-hscaler.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-kms.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-kms.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-layerblend.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-plane.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-plane.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-prg.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-prg.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-prv.h
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-tcon.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu-vscaler.c
create mode 100644 drivers/gpu/drm/imx/dpu/dpu.h
--
2.7.4
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Gasket.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
v7->v8:
* No change.
v6->v7:
* No change.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Improve compatible property by using enum instead of oneOf+const. (Rob)
* Add Rob's R-b tag.
v2->v3:
* No change.
v1->v2:
* Use new dt binding way to add clocks in the example.
.../bindings/display/imx/fsl,imx8qxp-prg.yaml | 60 ++++++++++++++++++++++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
new file mode 100644
index 00000000..3ff46e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-prg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Prefetch Resolve Gasket
+
+maintainers:
+ - Liu Ying <[email protected]>
+
+description: |
+ The i.MX8qm/qxp Prefetch Resolve Gasket (PRG) is a gasket interface between
+ RTRAM controller and Display Controller. The main function is to convert
+ the AXI interface to the RTRAM interface, which includes re-mapping the
+ ARADDR to a RTRAM address.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qxp-prg
+ - fsl,imx8qm-prg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: rtram clock
+ - description: apb clock
+
+ clock-names:
+ items:
+ - const: rtram
+ - const: apb
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ prg@56040000 {
+ compatible = "fsl,imx8qxp-prg";
+ reg = <0x56040000 0x10000>;
+ clocks = <&dc0_prg0_lpcg IMX_LPCG_CLK_0>,
+ <&dc0_prg0_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
--
2.7.4
This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
v7->v8:
* No change.
v6->v7:
* No change.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Improve compatible property by using enum instead of oneOf+const. (Rob)
* Add Rob's R-b tag.
v2->v3:
* No change.
v1->v2:
* Use new dt binding way to add clocks in the example.
.../bindings/display/imx/fsl,imx8qxp-dprc.yaml | 87 ++++++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
new file mode 100644
index 00000000..9e05c83
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dprc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Prefetch Resolve Channel
+
+maintainers:
+ - Liu Ying <[email protected]>
+
+description: |
+ The i.MX8qm/qxp Display Prefetch Resolve Channel(DPRC) is an engine which
+ fetches display data before the display pipeline needs the data to drive
+ pixels in the active display region. This data is transformed, or resolved,
+ from a variety of tiled buffer formats into linear format, if needed.
+ The DPR works with a double bank memory structure. This memory structure is
+ implemented in the Resolve Tile Memory(RTRAM) and the banks are referred to
+ as A and B. Each bank is either 4 or 8 lines high depending on the source
+ frame buffer format.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qxp-dpr-channel
+ - fsl,imx8qm-dpr-channel
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: apb clock
+ - description: b clock
+ - description: rtram clock
+
+ clock-names:
+ items:
+ - const: apb
+ - const: b
+ - const: rtram
+
+ fsl,sc-resource:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The SCU resource ID associated with this DPRC instance.
+
+ fsl,prgs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ List of phandle which points to Prefetch Resolve Gaskets(PRGs)
+ associated with this DPRC instance.
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - fsl,sc-resource
+ - fsl,prgs
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ dpr-channel@56100000 {
+ compatible = "fsl,imx8qxp-dpr-channel";
+ reg = <0x56100000 0x10000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dc0_dpr1_lpcg IMX_LPCG_CLK_4>,
+ <&dc0_dpr1_lpcg IMX_LPCG_CLK_5>,
+ <&dc0_rtram1_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "apb", "b", "rtram";
+ fsl,sc-resource = <IMX_SC_R_DC_0_VIDEO0>;
+ fsl,prgs = <&dc0_prg4>, <&dc0_prg5>;
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
--
2.7.4