This series enables miscellaneous hardware blocks to boot Wireless
Processor Subsystem (WPSS) on SC7280 SoC.
V2:
* place resets and num_resets adjacent to each other [Stephen]
* drop incorrect useage of tcsr_mutex_regs [Bjorn]
* Qualcomm is expected to drop master/slave naming from its mproc nodes
in future SoCs.
Sibi Sankar (5):
dt-bindings: mailbox: Add WPSS client index to IPCC
dt-bindings: reset: aoss: Add AOSS reset controller binding
dt-bindings: reset: pdc: Add PDC Global bindings
reset: qcom: Add PDC Global reset signals for WPSS
arm64: dts: qcom: sc7280: Add nodes to boot WPSS
.../devicetree/bindings/reset/qcom,aoss-reset.yaml | 5 +
.../devicetree/bindings/reset/qcom,pdc-global.yaml | 4 +
arch/arm64/boot/dts/qcom/sc7280.dtsi | 138 +++++++++++++++++++++
drivers/reset/reset-qcom-pdc.c | 62 +++++++--
include/dt-bindings/mailbox/qcom-ipcc.h | 1 +
include/dt-bindings/reset/qcom,sdm845-pdc.h | 2 +
6 files changed, 201 insertions(+), 11 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Add PDC Global reset signals for Wireless Processor Subsystem (WPSS)
on SC7280 SoCs.
Signed-off-by: Sibi Sankar <[email protected]>
---
v2:
* place resets and num_resets adjacent to each other [Stephen]
drivers/reset/reset-qcom-pdc.c | 62 ++++++++++++++++++++++++++++++++++--------
1 file changed, 51 insertions(+), 11 deletions(-)
diff --git a/drivers/reset/reset-qcom-pdc.c b/drivers/reset/reset-qcom-pdc.c
index ab74bccd4a5b..c10393f3ef8c 100644
--- a/drivers/reset/reset-qcom-pdc.c
+++ b/drivers/reset/reset-qcom-pdc.c
@@ -11,18 +11,26 @@
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
-#define RPMH_PDC_SYNC_RESET 0x100
+#define RPMH_SDM845_PDC_SYNC_RESET 0x100
+#define RPMH_SC7280_PDC_SYNC_RESET 0x1000
struct qcom_pdc_reset_map {
u8 bit;
};
+struct qcom_pdc_reset_desc {
+ const struct qcom_pdc_reset_map *resets;
+ size_t num_resets;
+ unsigned int offset;
+};
+
struct qcom_pdc_reset_data {
struct reset_controller_dev rcdev;
struct regmap *regmap;
+ const struct qcom_pdc_reset_desc *desc;
};
-static const struct regmap_config sdm845_pdc_regmap_config = {
+static const struct regmap_config pdc_regmap_config = {
.name = "pdc-reset",
.reg_bits = 32,
.reg_stride = 4,
@@ -44,6 +52,33 @@ static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
[PDC_MODEM_SYNC_RESET] = {9},
};
+static const struct qcom_pdc_reset_desc sdm845_pdc_reset_desc = {
+ .resets = sdm845_pdc_resets,
+ .offset = RPMH_SDM845_PDC_SYNC_RESET,
+ .num_resets = ARRAY_SIZE(sdm845_pdc_resets),
+};
+
+static const struct qcom_pdc_reset_map sc7280_pdc_resets[] = {
+ [PDC_APPS_SYNC_RESET] = {0},
+ [PDC_SP_SYNC_RESET] = {1},
+ [PDC_AUDIO_SYNC_RESET] = {2},
+ [PDC_SENSORS_SYNC_RESET] = {3},
+ [PDC_AOP_SYNC_RESET] = {4},
+ [PDC_DEBUG_SYNC_RESET] = {5},
+ [PDC_GPU_SYNC_RESET] = {6},
+ [PDC_DISPLAY_SYNC_RESET] = {7},
+ [PDC_COMPUTE_SYNC_RESET] = {8},
+ [PDC_MODEM_SYNC_RESET] = {9},
+ [PDC_WLAN_RF_SYNC_RESET] = {10},
+ [PDC_WPSS_SYNC_RESET] = {11},
+};
+
+static const struct qcom_pdc_reset_desc sc7280_pdc_reset_desc = {
+ .resets = sc7280_pdc_resets,
+ .offset = RPMH_SC7280_PDC_SYNC_RESET,
+ .num_resets = ARRAY_SIZE(sc7280_pdc_resets),
+};
+
static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
struct reset_controller_dev *rcdev)
{
@@ -54,19 +89,18 @@ static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
unsigned long idx)
{
struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
+ const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
- return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
- BIT(sdm845_pdc_resets[idx].bit),
- BIT(sdm845_pdc_resets[idx].bit));
+ return regmap_update_bits(data->regmap, data->desc->offset, BIT(map->bit), BIT(map->bit));
}
static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
unsigned long idx)
{
struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
+ const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
- return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
- BIT(sdm845_pdc_resets[idx].bit), 0);
+ return regmap_update_bits(data->regmap, data->desc->offset, BIT(map->bit), 0);
}
static const struct reset_control_ops qcom_pdc_reset_ops = {
@@ -76,22 +110,27 @@ static const struct reset_control_ops qcom_pdc_reset_ops = {
static int qcom_pdc_reset_probe(struct platform_device *pdev)
{
+ const struct qcom_pdc_reset_desc *desc;
struct qcom_pdc_reset_data *data;
struct device *dev = &pdev->dev;
void __iomem *base;
struct resource *res;
+ desc = device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -EINVAL;
+
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
+ data->desc = desc;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
- data->regmap = devm_regmap_init_mmio(dev, base,
- &sdm845_pdc_regmap_config);
+ data->regmap = devm_regmap_init_mmio(dev, base, &pdc_regmap_config);
if (IS_ERR(data->regmap)) {
dev_err(dev, "Unable to initialize regmap\n");
return PTR_ERR(data->regmap);
@@ -99,14 +138,15 @@ static int qcom_pdc_reset_probe(struct platform_device *pdev)
data->rcdev.owner = THIS_MODULE;
data->rcdev.ops = &qcom_pdc_reset_ops;
- data->rcdev.nr_resets = ARRAY_SIZE(sdm845_pdc_resets);
+ data->rcdev.nr_resets = desc->num_resets;
data->rcdev.of_node = dev->of_node;
return devm_reset_controller_register(dev, &data->rcdev);
}
static const struct of_device_id qcom_pdc_reset_of_match[] = {
- { .compatible = "qcom,sdm845-pdc-global" },
+ { .compatible = "qcom,sc7280-pdc-global", .data = &sc7280_pdc_reset_desc },
+ { .compatible = "qcom,sdm845-pdc-global", .data = &sdm845_pdc_reset_desc },
{}
};
MODULE_DEVICE_TABLE(of, qcom_pdc_reset_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Add miscellaneous nodes to boot the Wireless Processor Subsystem (WPSS) on
SC7280 SoCs.
Signed-off-by: Sibi Sankar <[email protected]>
---
v2:
* drop incorrect useage of tcsr_mutex_regs [Bjorn]
arch/arm64/boot/dts/qcom/sc7280.dtsi | 138 +++++++++++++++++++++++++++++++++++
1 file changed, 138 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 2cc478553935..5e0ae4a1c433 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -11,6 +11,8 @@
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/reset/qcom,sdm845-aoss.h>
+#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@@ -51,6 +53,11 @@
no-map;
};
+ smem_mem: memory@80900000 {
+ reg = <0x0 0x80900000 0x0 0x200000>;
+ no-map;
+ };
+
cpucp_mem: memory@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
@@ -251,6 +258,119 @@
};
};
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-mpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ ipa_smp2p_out: ipa-ap-to-modem {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ ipa_smp2p_in: ipa-modem-to-ap {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-wpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <617>, <616>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <13>;
+
+ wpss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wpss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
@@ -812,6 +932,12 @@
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex", "syscon";
+ reg = <0 0x01f40000 0 0x40000>;
+ #hwlock-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7280-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
@@ -825,6 +951,18 @@
interrupt-controller;
};
+ pdc_reset: reset-controller@b5e0000 {
+ compatible = "qcom,sc7280-pdc-global";
+ reg = <0 0x0b5e0000 0 0x20000>;
+ #reset-cells = <1>;
+ };
+
+ aoss_reset: reset-controller@c2a0000 {
+ compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
+ reg = <0 0x0c2a0000 0 0x31000>;
+ #reset-cells = <1>;
+ };
+
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sc7280-aoss-qmp";
reg = <0 0x0c300000 0 0x100000>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Add PDC Global reset controller bindings for SC7280 SoCs.
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Sibi Sankar <[email protected]>
---
Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml | 4 ++++
include/dt-bindings/reset/qcom,sdm845-pdc.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml b/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
index d7d8cec9419f..831ea8d5d83f 100644
--- a/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
+++ b/Documentation/devicetree/bindings/reset/qcom,pdc-global.yaml
@@ -21,6 +21,10 @@ properties:
- const: "qcom,sc7180-pdc-global"
- const: "qcom,sdm845-pdc-global"
+ - description: on SC7280 SoCs the following compatibles must be specified
+ items:
+ - const: "qcom,sc7280-pdc-global"
+
- description: on SDM845 SoCs the following compatibles must be specified
items:
- const: "qcom,sdm845-pdc-global"
diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h
index 53c37f9c319a..03a0c0eb8147 100644
--- a/include/dt-bindings/reset/qcom,sdm845-pdc.h
+++ b/include/dt-bindings/reset/qcom,sdm845-pdc.h
@@ -16,5 +16,7 @@
#define PDC_DISPLAY_SYNC_RESET 7
#define PDC_COMPUTE_SYNC_RESET 8
#define PDC_MODEM_SYNC_RESET 9
+#define PDC_WLAN_RF_SYNC_RESET 10
+#define PDC_WPSS_SYNC_RESET 11
#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Hi Sibi,
On Tue, 2021-04-27 at 13:03 +0530, Sibi Sankar wrote:
> Add PDC Global reset signals for Wireless Processor Subsystem (WPSS)
> on SC7280 SoCs.
>
> Signed-off-by: Sibi Sankar <[email protected]>
> ---
>
> v2:
> * place resets and num_resets adjacent to each other [Stephen]
[...]
> +struct qcom_pdc_reset_desc {
> + const struct qcom_pdc_reset_map *resets;
> + size_t num_resets;
> + unsigned int offset;
> +};
[...]
For consistency, please do the same here:
> +static const struct qcom_pdc_reset_desc sdm845_pdc_reset_desc = {
> + .resets = sdm845_pdc_resets,
> + .offset = RPMH_SDM845_PDC_SYNC_RESET,
> + .num_resets = ARRAY_SIZE(sdm845_pdc_resets),
> +};
[...]
and here:
> +static const struct qcom_pdc_reset_desc sc7280_pdc_reset_desc = {
> + .resets = sc7280_pdc_resets,
> + .offset = RPMH_SC7280_PDC_SYNC_RESET,
> + .num_resets = ARRAY_SIZE(sc7280_pdc_resets),
> +};
[...]
> @@ -54,19 +89,18 @@ static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
> unsigned long idx)
> {
> struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
> + const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
>
> - return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
> - BIT(sdm845_pdc_resets[idx].bit),
> - BIT(sdm845_pdc_resets[idx].bit));
> + return regmap_update_bits(data->regmap, data->desc->offset, BIT(map->bit), BIT(map->bit));
> }
Why not go one step further:
u32 mask = BIT(data->desc->resets[idx].bit);
return regmap_update_bits(data->regmap, data->desc->offset, mask, mask);
That seems to be a common pattern in other qcom drivers.
Either way, with the above reset/num_reset changes:
Reviewed-by: Philipp Zabel <[email protected]>
Also,
Acked-by: Philipp Zabel <[email protected]>
for the whole series to go through the qcom tree, or let me know if you
want me to pick up patches 2-4 next round.
regards
Philipp
Hey Philipp,
Thanks for the review. Will get them
fixed in the next re-spin.
On 2021-04-27 13:28, Philipp Zabel wrote:
> Hi Sibi,
>
> On Tue, 2021-04-27 at 13:03 +0530, Sibi Sankar wrote:
>> Add PDC Global reset signals for Wireless Processor Subsystem (WPSS)
>> on SC7280 SoCs.
>>
>> Signed-off-by: Sibi Sankar <[email protected]>
>> ---
>>
>> v2:
>> * place resets and num_resets adjacent to each other [Stephen]
> [...]
>> +struct qcom_pdc_reset_desc {
>> + const struct qcom_pdc_reset_map *resets;
>> + size_t num_resets;
>> + unsigned int offset;
>> +};
> [...]
>
> For consistency, please do the same here:
>
>> +static const struct qcom_pdc_reset_desc sdm845_pdc_reset_desc = {
>> + .resets = sdm845_pdc_resets,
>> + .offset = RPMH_SDM845_PDC_SYNC_RESET,
>> + .num_resets = ARRAY_SIZE(sdm845_pdc_resets),
>> +};
> [...]
>
> and here:
>
>> +static const struct qcom_pdc_reset_desc sc7280_pdc_reset_desc = {
>> + .resets = sc7280_pdc_resets,
>> + .offset = RPMH_SC7280_PDC_SYNC_RESET,
>> + .num_resets = ARRAY_SIZE(sc7280_pdc_resets),
>> +};
>
> [...]
>> @@ -54,19 +89,18 @@ static int qcom_pdc_control_assert(struct
>> reset_controller_dev *rcdev,
>> unsigned long idx)
>> {
>> struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
>> + const struct qcom_pdc_reset_map *map = &data->desc->resets[idx];
>>
>> - return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
>> - BIT(sdm845_pdc_resets[idx].bit),
>> - BIT(sdm845_pdc_resets[idx].bit));
>> + return regmap_update_bits(data->regmap, data->desc->offset,
>> BIT(map->bit), BIT(map->bit));
>> }
>
> Why not go one step further:
>
> u32 mask = BIT(data->desc->resets[idx].bit);
>
> return regmap_update_bits(data->regmap, data->desc->offset, mask,
> mask);
>
> That seems to be a common pattern in other qcom drivers.
will send out a separate patch for
the other reset driver.
> Either way, with the above reset/num_reset changes:
>
> Reviewed-by: Philipp Zabel <[email protected]>
>
> Also,
>
> Acked-by: Philipp Zabel <[email protected]>
>
> for the whole series to go through the qcom tree, or let me know if you
> want me to pick up patches 2-4 next round.
>
> regards
> Philipp
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
On Tue 27 Apr 02:58 CDT 2021, Philipp Zabel wrote:
> Hi Sibi,
>
> On Tue, 2021-04-27 at 13:03 +0530, Sibi Sankar wrote:
[..]
> Acked-by: Philipp Zabel <[email protected]>
>
> for the whole series to go through the qcom tree, or let me know if you
> want me to pick up patches 2-4 next round.
>
Philipp, please do take patch 2-4 through your tree, that way we avoid
any potential conflicts in the driver - and things will come together
nicely for validation in linux-next anyways.
Regards,
Bjorn
Hi Bjorn,
On Mon, 2021-05-31 at 17:04 -0500, Bjorn Andersson wrote:
> On Tue 27 Apr 02:58 CDT 2021, Philipp Zabel wrote:
>
> > Hi Sibi,
> >
> > On Tue, 2021-04-27 at 13:03 +0530, Sibi Sankar wrote:
> [..]
> > Acked-by: Philipp Zabel <[email protected]>
> >
> > for the whole series to go through the qcom tree, or let me know if you
> > want me to pick up patches 2-4 next round.
> >
>
> Philipp, please do take patch 2-4 through your tree, that way we avoid
> any potential conflicts in the driver - and things will come together
> nicely for validation in linux-next anyways.
FTR, Patches 2-4 of v3 are now applied to reset/next.
regards
Philipp