The patch series adds support for DDR/L3 Scaling on SC7280 SoCs.
V2:
* Add a new opp table for cpu 7 to account for the additional frequencies
supported by it.
Depends on the following patch series:
L3 Provider Support: https://lore.kernel.org/lkml/[email protected]/
CPUfreq Support: https://lore.kernel.org/lkml/[email protected]/
RPMH Provider Support: https://lore.kernel.org/lkml/[email protected]/
It also depends on L3 and cpufreq dt nodes from the ^^ series to not have
overlapping memory regions.
Sibi Sankar (2):
cpufreq: blacklist SC7280 in cpufreq-dt-platdev
arm64: dts: qcom: sc7280: Add cpu OPP tables
arch/arm64/boot/dts/qcom/sc7280.dtsi | 215 +++++++++++++++++++++++++++++++++++
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
2 files changed, 216 insertions(+)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Add SC7280 to cpufreq-dt-platdev blacklist since the actual scaling is
handled by the 'qcom-cpufreq-hw' driver.
Signed-off-by: Sibi Sankar <[email protected]>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 5e07065ec22f..345418b8250e 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -137,6 +137,7 @@ static const struct of_device_id blacklist[] __initconst = {
{ .compatible = "qcom,msm8996", },
{ .compatible = "qcom,qcs404", },
{ .compatible = "qcom,sc7180", },
+ { .compatible = "qcom,sc7280", },
{ .compatible = "qcom,sdm845", },
{ .compatible = "st,stih407", },
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Add OPP tables required to scale DDR/L3 per freq-domain on SC7280 SoCs.
Signed-off-by: Sibi Sankar <[email protected]>
---
v2:
* Add a new opp table for cpu 7 to account for the additional frequencies
supported by it.
arch/arm64/boot/dts/qcom/sc7280.dtsi | 215 +++++++++++++++++++++++++++++++++++
1 file changed, 215 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 0bb835aeae33..34e9df7ea683 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -71,6 +72,9 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
+ <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
@@ -90,6 +94,9 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_100>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
+ <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
@@ -106,6 +113,9 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_200>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
+ <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
@@ -122,6 +132,9 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_300>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
+ <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
@@ -138,6 +151,9 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_400>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
+ <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_400: l2-cache {
compatible = "cache";
@@ -154,6 +170,9 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_500>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
+ <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_500: l2-cache {
compatible = "cache";
@@ -170,6 +189,9 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_600>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
+ <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
@@ -186,6 +208,9 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_700>;
+ operating-points-v2 = <&cpu7_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
+ <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 2>;
L2_700: l2-cache {
compatible = "cache";
@@ -248,6 +273,196 @@
};
};
+ cpu0_opp_table: cpu0_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu0_opp1: opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-peak-kBps = <800000 9600000>;
+ };
+
+ cpu0_opp2: opp-691200000 {
+ opp-hz = /bits/ 64 <691200000>;
+ opp-peak-kBps = <800000 17817600>;
+ };
+
+ cpu0_opp3: opp-806400000 {
+ opp-hz = /bits/ 64 <806400000>;
+ opp-peak-kBps = <800000 20889600>;
+ };
+
+ cpu0_opp4: opp-940800000 {
+ opp-hz = /bits/ 64 <940800000>;
+ opp-peak-kBps = <1804000 24576000>;
+ };
+
+ cpu0_opp5: opp-1152000000 {
+ opp-hz = /bits/ 64 <1152000000>;
+ opp-peak-kBps = <2188000 27033600>;
+ };
+
+ cpu0_opp6: opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-peak-kBps = <2188000 33792000>;
+ };
+
+ cpu0_opp7: opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-peak-kBps = <3072000 38092800>;
+ };
+
+ cpu0_opp8: opp-1651200000 {
+ opp-hz = /bits/ 64 <1651200000>;
+ opp-peak-kBps = <3072000 41779200>;
+ };
+
+ cpu0_opp9: opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <4068000 48537600>;
+ };
+
+ cpu0_opp10: opp-1958400000 {
+ opp-hz = /bits/ 64 <1958400000>;
+ opp-peak-kBps = <4068000 48537600>;
+ };
+ };
+
+ cpu4_opp_table: cpu4_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu4_opp1: opp-691200000 {
+ opp-hz = /bits/ 64 <691200000>;
+ opp-peak-kBps = <1804000 9600000>;
+ };
+
+ cpu4_opp2: opp-940800000 {
+ opp-hz = /bits/ 64 <940800000>;
+ opp-peak-kBps = <2188000 17817600>;
+ };
+
+ cpu4_opp3: opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ opp-peak-kBps = <4068000 24576000>;
+ };
+
+ cpu4_opp4: opp-1344000000 {
+ opp-hz = /bits/ 64 <1344000000>;
+ opp-peak-kBps = <4068000 24576000>;
+ };
+
+ cpu4_opp5: opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-peak-kBps = <4068000 24576000>;
+ };
+
+ cpu4_opp6: opp-1651200000 {
+ opp-hz = /bits/ 64 <1651200000>;
+ opp-peak-kBps = <6220000 38092800>;
+ };
+
+ cpu4_opp7: opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-peak-kBps = <6220000 44851200>;
+ };
+
+ cpu4_opp8: opp-2054400000 {
+ opp-hz = /bits/ 64 <2054400000>;
+ opp-peak-kBps = <6220000 44851200>;
+ };
+
+ cpu4_opp9: opp-2112000000 {
+ opp-hz = /bits/ 64 <2112000000>;
+ opp-peak-kBps = <6220000 44851200>;
+ };
+
+ cpu4_opp10: opp-2131200000 {
+ opp-hz = /bits/ 64 <2131200000>;
+ opp-peak-kBps = <6220000 44851200>;
+ };
+
+ cpu4_opp11: opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-peak-kBps = <6220000 44851200>;
+ };
+
+ cpu4_opp12: opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-peak-kBps = <8532000 48537600>;
+ };
+ };
+
+ cpu7_opp_table: cpu7_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu7_opp1: opp-806400000 {
+ opp-hz = /bits/ 64 <806400000>;
+ opp-peak-kBps = <1804000 9600000>;
+ };
+
+ cpu7_opp2: opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-peak-kBps = <2188000 17817600>;
+ };
+
+ cpu7_opp3: opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-peak-kBps = <4068000 24576000>;
+ };
+
+ cpu7_opp4: opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-peak-kBps = <4068000 24576000>;
+ };
+
+ cpu7_opp5: opp-1766400000 {
+ opp-hz = /bits/ 64 <1766400000>;
+ opp-peak-kBps = <6220000 38092800>;
+ };
+
+ cpu7_opp6: opp-1862400000 {
+ opp-hz = /bits/ 64 <1862400000>;
+ opp-peak-kBps = <6220000 38092800>;
+ };
+
+ cpu7_opp7: opp-2035200000 {
+ opp-hz = /bits/ 64 <2035200000>;
+ opp-peak-kBps = <6220000 38092800>;
+ };
+
+ cpu7_opp8: opp-2112000000 {
+ opp-hz = /bits/ 64 <2112000000>;
+ opp-peak-kBps = <6220000 44851200>;
+ };
+
+ cpu7_opp9: opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-peak-kBps = <6220000 44851200>;
+ };
+
+ cpu7_opp10: opp-2380800000 {
+ opp-hz = /bits/ 64 <2380800000>;
+ opp-peak-kBps = <6832000 44851200>;
+ };
+
+ cpu7_opp11: opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-peak-kBps = <8532000 48537600>;
+ };
+
+ cpu7_opp12: opp-2515200000 {
+ opp-hz = /bits/ 64 <2515200000>;
+ opp-peak-kBps = <8532000 48537600>;
+ };
+
+ cpu7_opp13: opp-2707200000 {
+ opp-hz = /bits/ 64 <2707200000>;
+ opp-peak-kBps = <8532000 48537600>;
+ };
+ };
+
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Hi,
On Mon, May 3, 2021 at 11:59 PM Sibi Sankar <[email protected]> wrote:
>
> + cpu0_opp_table: cpu0_opp_table {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + cpu0_opp1: opp-300000000 {
It seems like it might be nicer to give the node labels a less
arbitrary name. How about?
cpu0_opp_300mhz: opp-300000000
That has advantes:
* If, for some reason, you have to mess with some operating point in
another dts it'll be less fragile.
* It'll make diffing easier between SoCs.
* If you end up putting a new operating point in the middle you don't
need to rename everything below.
Other than that, I can't say that I'm a huge expert on the
interconnect stuff and whether those make sense, but I'm still OK
with:
Reviewed-by: Douglas Anderson <[email protected]>
Hi,
On Mon, May 3, 2021 at 11:58 PM Sibi Sankar <[email protected]> wrote:
>
> Add SC7280 to cpufreq-dt-platdev blacklist since the actual scaling is
> handled by the 'qcom-cpufreq-hw' driver.
>
> Signed-off-by: Sibi Sankar <[email protected]>
> ---
> drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Douglas Anderson <[email protected]>
Hey Doug,
Thanks for the review!
On 2021-05-05 01:32, Doug Anderson wrote:
> Hi,
>
> On Mon, May 3, 2021 at 11:59 PM Sibi Sankar <[email protected]>
> wrote:
>>
>> + cpu0_opp_table: cpu0_opp_table {
>> + compatible = "operating-points-v2";
>> + opp-shared;
>> +
>> + cpu0_opp1: opp-300000000 {
>
> It seems like it might be nicer to give the node labels a less
> arbitrary name. How about?
>
> cpu0_opp_300mhz: opp-300000000
>
> That has advantes:
>
> * If, for some reason, you have to mess with some operating point in
> another dts it'll be less fragile.
>
> * It'll make diffing easier between SoCs.
>
> * If you end up putting a new operating point in the middle you don't
> need to rename everything below.
sure makes sense, will fix it in v3.
>
> Other than that, I can't say that I'm a huge expert on the
> interconnect stuff and whether those make sense, but I'm still OK
> with:
>
> Reviewed-by: Douglas Anderson <[email protected]>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.