From: Nina Wu <[email protected]>
For new ICs, there are multiple devapc HWs for different subsys.
We add a field 'vio-idx-num' in DT to indicate the number of
devices controlled by each devapc.
To be backward compatible with old ICs which have only one devapc
HW, this field is not required. The 'vio-idx-num' info will be set
in compatible data instead.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Nina Wu <[email protected]>
---
Documentation/devicetree/bindings/soc/mediatek/devapc.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
index 31e4d3c..69abd03 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
@@ -20,11 +20,16 @@ properties:
compatible:
enum:
- mediatek,mt6779-devapc
+ - mediatek,mt8192-devapc
reg:
description: The base address of devapc register bank
maxItems: 1
+ mediatek,vio-idx-num:
+ description: The number of the devices controlled by devapc
+ $ref: /schemas/types.yaml#/definitions/uint32
+
interrupts:
description: A single interrupt specifier
maxItems: 1
--
2.6.4
From: Nina Wu <[email protected]>
There are 3 debug info registers in new ICs while in legacy ones,
we have only 2. We add a 'version' field in compatible data to
decide how we extract the debug info.
Signed-off-by: Nina Wu <[email protected]>
---
drivers/soc/mediatek/mtk-devapc.c | 43 +++++++++++++++++++++++++++++++++++----
1 file changed, 39 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
index f5d63c5..bdc8fe9 100644
--- a/drivers/soc/mediatek/mtk-devapc.c
+++ b/drivers/soc/mediatek/mtk-devapc.c
@@ -26,12 +26,24 @@ struct mtk_devapc_vio_dbgs {
u32 addr_h:4;
u32 resv:4;
} dbg0_bits;
+
+ struct {
+ u32 dmnid:6;
+ u32 vio_w:1;
+ u32 vio_r:1;
+ u32 addr_h:4;
+ u32 resv:20;
+ } dbg0_bits_ver2;
};
u32 vio_dbg1;
+ u32 vio_dbg2;
};
struct mtk_devapc_data {
+ /* architecture version */
+ u32 version;
+
/* default numbers of violation index */
u32 vio_idx_num;
@@ -40,6 +52,7 @@ struct mtk_devapc_data {
u32 vio_sta_offset;
u32 vio_dbg0_offset;
u32 vio_dbg1_offset;
+ u32 vio_dbg2_offset;
u32 apc_con_offset;
u32 vio_shift_sta_offset;
u32 vio_shift_sel_offset;
@@ -163,22 +176,43 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
struct mtk_devapc_vio_dbgs vio_dbgs;
void __iomem *vio_dbg0_reg;
void __iomem *vio_dbg1_reg;
+ void __iomem *vio_dbg2_reg;
+ u32 vio_addr, bus_id, domain_id;
+ u32 vio_w, vio_r;
vio_dbg0_reg = ctx->base + ctx->data->vio_dbg0_offset;
vio_dbg1_reg = ctx->base + ctx->data->vio_dbg1_offset;
+ vio_dbg2_reg = ctx->base + ctx->data->vio_dbg2_offset;
vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg);
vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg);
+ if (ctx->data->version == 2U)
+ vio_dbgs.vio_dbg2 = readl(vio_dbg2_reg);
+
+ if (ctx->data->version == 1U) {
+ /* arch version 1 */
+ bus_id = vio_dbgs.dbg0_bits.mstid;
+ vio_addr = vio_dbgs.vio_dbg1;
+ domain_id = vio_dbgs.dbg0_bits.dmnid;
+ vio_w = vio_dbgs.dbg0_bits.vio_w;
+ vio_r = vio_dbgs.dbg0_bits.vio_r;
+ } else {
+ /* arch version 2 */
+ bus_id = vio_dbgs.vio_dbg1;
+ vio_addr = vio_dbgs.vio_dbg2;
+ domain_id = vio_dbgs.dbg0_bits_ver2.dmnid;
+ vio_w = vio_dbgs.dbg0_bits_ver2.vio_w;
+ vio_r = vio_dbgs.dbg0_bits_ver2.vio_r;
+ }
/* Print violation information */
- if (vio_dbgs.dbg0_bits.vio_w)
+ if (vio_w)
dev_info(ctx->dev, "Write Violation\n");
- else if (vio_dbgs.dbg0_bits.vio_r)
+ else if (vio_r)
dev_info(ctx->dev, "Read Violation\n");
dev_info(ctx->dev, "Bus ID:0x%x, Dom ID:0x%x, Vio Addr:0x%x\n",
- vio_dbgs.dbg0_bits.mstid, vio_dbgs.dbg0_bits.dmnid,
- vio_dbgs.vio_dbg1);
+ bus_id, domain_id, vio_addr);
}
/*
@@ -219,6 +253,7 @@ static void stop_devapc(struct mtk_devapc_context *ctx)
}
static const struct mtk_devapc_data devapc_mt6779 = {
+ .version = 1,
.vio_idx_num = 511,
.vio_mask_offset = 0x0,
.vio_sta_offset = 0x400,
--
2.6.4