Add display port supported node for sc7280. Also correct dp-phy node
tx/rx/pcs/tx2/rx2 base reg address to fix aux channel read/write
failure issue.
Signed-off-by: Kuogee Hsieh <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 9 +++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 98 +++++++++++++++++++++++++++++---
2 files changed, 100 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts
index b1cf70e..4aea369 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts
@@ -202,3 +202,12 @@ ap_h1_spi: &spi14 {};
backlight = <&backlight>;
};
};
+
+&msm_dp {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp_hot_plug_det>;
+ data-lanes = <0 1>;
+ vdda-1p2-supply = <&vreg_l6b_1p2>;
+ vdda-0p9-supply = <&vreg_l1b_0p8>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index c29226b..a350d84 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2918,15 +2918,11 @@
dp_phy: dp-phy@88ea200 {
reg = <0 0x088ea200 0 0x200>,
<0 0x088ea400 0 0x200>,
- <0 0x088eac00 0 0x400>,
+ <0 0x088eaa00 0 0x200>,
<0 0x088ea600 0 0x200>,
- <0 0x088ea800 0 0x200>,
- <0 0x088eaa00 0 0x100>;
+ <0 0x088ea800 0 0x200>;
#phy-cells = <0>;
#clock-cells = <1>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
};
};
@@ -3202,6 +3198,13 @@
remote-endpoint = <&edp_in>;
};
};
+
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&dp_in>;
+ };
+ };
};
mdp_opp_table: mdp-opp-table {
@@ -3389,6 +3392,74 @@
};
};
};
+
+ msm_dp: displayport-controller@ae90000 {
+ status = "disabled";
+ compatible = "qcom,sc7180-dp";
+
+ reg = <0 0x0ae90000 0 0x1400>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <12 IRQ_TYPE_NONE>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ clock-names = "core_iface", "core_aux", "ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+ #clock-cells = <1>;
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
+ phys = <&dp_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SC7180_CX>;
+
+ #sound-dai-cells = <0>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dp_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_out: endpoint { };
+ };
+ };
+
+ dp_opp_table: dp-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
};
dispcc: clock-controller@af00000 {
@@ -3398,7 +3469,8 @@
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&dsi_phy 0>,
<&dsi_phy 1>,
- <0>, <0>,
+ <&dp_phy 0>,
+ <&dp_phy 1>,
<&msm_edp 0>,
<&msm_edp 1>;
clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
@@ -3525,6 +3597,18 @@
};
};
+ dp_hot_plug_det: dp-hot-plug-det {
+ pinmux {
+ pins = "gpio47";
+ function = "dp_hot";
+ };
+
+ pinconf {
+ pins = "gpio47";
+ bias-disable;
+ };
+ };
+
qspi_clk: qspi-clk {
pins = "gpio14";
function = "qspi_clk";
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Hi Kuogee,
On 8/25/21 1:20 AM, Kuogee Hsieh wrote:
> [..]
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index c29226b..a350d84 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> [..]
> + msm_dp: displayport-controller@ae90000 {
> + status = "disabled";
> + compatible = "qcom,sc7180-dp";
> +
> + reg = <0 0x0ae90000 0 0x1400>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <12 IRQ_TYPE_NONE>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
> + clock-names = "core_iface", "core_aux", "ctrl_link",
> + "ctrl_link_iface", "stream_pixel";
> + #clock-cells = <1>;
> + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
> + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
> + phys = <&dp_phy>;
> + phy-names = "dp";
> +
> + operating-points-v2 = <&dp_opp_table>;
> + power-domains = <&rpmhpd SC7180_CX>;
Despite having the same value as SC7180_CX, you may want to use
SC7280_CX here.
- Marijn
Quoting Kuogee Hsieh (2021-08-24 16:20:26)
> Add display port supported node for sc7280. Also correct dp-phy node
> tx/rx/pcs/tx2/rx2 base reg address to fix aux channel read/write
> failure issue.
>
> Signed-off-by: Kuogee Hsieh <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 9 +++
Please split the idp diff from the sc7280.dts diff so that there are two
patches instead of one. It helps with ignoring the idp diff.
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 98 +++++++++++++++++++++++++++++---
> 2 files changed, 100 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts
> index b1cf70e..4aea369 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts
> @@ -202,3 +202,12 @@ ap_h1_spi: &spi14 {};
> backlight = <&backlight>;
> };
> };
> +
> +&msm_dp {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&dp_hot_plug_det>;
> + data-lanes = <0 1>;
> + vdda-1p2-supply = <&vreg_l6b_1p2>;
> + vdda-0p9-supply = <&vreg_l1b_0p8>;
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index c29226b..a350d84 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2918,15 +2918,11 @@
> dp_phy: dp-phy@88ea200 {
> reg = <0 0x088ea200 0 0x200>,
> <0 0x088ea400 0 0x200>,
> - <0 0x088eac00 0 0x400>,
> + <0 0x088eaa00 0 0x200>,
> <0 0x088ea600 0 0x200>,
> - <0 0x088ea800 0 0x200>,
> - <0 0x088eaa00 0 0x100>;
> + <0 0x088ea800 0 0x200>;
So this was wrong? Best to split that out into another patch with the
appropriate Fixes tag.
> #phy-cells = <0>;
> #clock-cells = <1>;
> - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> - clock-names = "pipe0";
> - clock-output-names = "usb3_phy_pipe_clk_src";
And then mention this part in the commit text of the fixing patch.
> };
> };
>
> @@ -3389,6 +3392,74 @@
> };
> };
> };
> +
> + msm_dp: displayport-controller@ae90000 {
> + status = "disabled";
> + compatible = "qcom,sc7180-dp";
Can we add qcom,sc7280-dp as well? Just in case anything is wrong with
sc7280 specifically.
> +
> + reg = <0 0x0ae90000 0 0x1400>;
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <12 IRQ_TYPE_NONE>;
Drop IRQ_TYPE_NONE per the binding it is one cell, not two.
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
> + clock-names = "core_iface", "core_aux", "ctrl_link",
> + "ctrl_link_iface", "stream_pixel";
Can we get clock-names on one line matching the clocks property please?
That makes it easier to match it up between the two properties.
> + #clock-cells = <1>;
> + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
> + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
> + phys = <&dp_phy>;
> + phy-names = "dp";
> +
> + operating-points-v2 = <&dp_opp_table>;
> + power-domains = <&rpmhpd SC7180_CX>;
> +
> + #sound-dai-cells = <0>;
Nitpick: Newline here.
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + dp_in: endpoint {
> + remote-endpoint = <&dpu_intf0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dp_out: endpoint { };
> + };
> + };
> +
> + dp_opp_table: dp-opp-table {
dp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-160000000 {
> + opp-hz = /bits/ 64 <160000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> };
>
> dispcc: clock-controller@af00000 {
> @@ -3398,7 +3469,8 @@
> <&gcc GCC_DISP_GPLL0_CLK_SRC>,
> <&dsi_phy 0>,
> <&dsi_phy 1>,
> - <0>, <0>,
> + <&dp_phy 0>,
> + <&dp_phy 1>,
> <&msm_edp 0>,
> <&msm_edp 1>;
> clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
> @@ -3525,6 +3597,18 @@
> };
> };
>
> + dp_hot_plug_det: dp-hot-plug-det {
> + pinmux {
> + pins = "gpio47";
> + function = "dp_hot";
> + };
> +
> + pinconf {
> + pins = "gpio47";
> + bias-disable;
> + };
Combine these two nodes (pinmux and pinconf) into one please.
dp_hot_plug_det: dp-hot-plug-det {
pins = "gpio47";
function = "dp_hot";
bias-disable;
};
> + };
> +
> qspi_clk: qspi-clk {
> pins = "gpio14";
> function = "qspi_clk";