The blk-ctrl and the GPCv2 in the i.MX8MN is similar but slightly different to that
of the i.MX8MM. This series is based on work from Lucas Stach for i.MX8MM, but
adapted for i.MX8MN. With the additional power domains and blk-ctrl enabled,
additional peripherals like gpu and USB can be enabled.
V2: Add mising patches for expanding GPCv2 which are necessary
to make the blk-ctl operate.
Fix clk names
Fix missing references to structures in blk-ctl driver to link
them to the device tree.
Adam Ford (9):
soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled
soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn
dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains
dt-bindings: soc: add binding for i.MX8MN DISP blk-ctrl
soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl
arm64: dts: imx8mn: add GPC node
arm64: dts: imx8mn: put USB controller into power-domains
arm64: dts: imx8mn: add DISP blk-ctrl
arm64: dts: imx8mn: Enable GPU
.../soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 97 +++++++++++++++++
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 103 ++++++++++++++++++
drivers/soc/imx/gpcv2.c | 26 +++++
drivers/soc/imx/imx8m-blk-ctrl.c | 75 ++++++++++++-
include/dt-bindings/power/imx8mn-power.h | 5 +
5 files changed, 305 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
--
2.25.1
Like the i.MX8MM, keep the gpumix clocks running when the
domain is active.
Signed-off-by: Adam Ford <[email protected]>
---
drivers/soc/imx/gpcv2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index b8d52d8d29db..95f05575f843 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -840,6 +840,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
.hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
},
.pgc = BIT(IMX8MN_PGC_GPUMIX),
+ .keep_clocks = true,
},
};
--
2.25.1
The dispmix will be needed for the blkctl driver, so add it
to the gpcv2.
Signed-off-by: Adam Ford <[email protected]>
---
drivers/soc/imx/gpcv2.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 95f05575f843..7b568cf39a5a 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -842,6 +842,31 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
.pgc = BIT(IMX8MN_PGC_GPUMIX),
.keep_clocks = true,
},
+
+ [IMX8MN_POWER_DOMAIN_DISPMIX] = {
+ .genpd = {
+ .name = "dispmix",
+ },
+ .bits = {
+ .pxx = IMX8MN_DISPMIX_SW_Pxx_REQ,
+ .map = IMX8MN_DISPMIX_A53_DOMAIN,
+ .hskreq = IMX8MN_DISPMIX_HSK_PWRDNREQN,
+ .hskack = IMX8MN_DISPMIX_HSK_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MN_PGC_DISPMIX),
+ .keep_clocks = true,
+ },
+
+ [IMX8MN_POWER_DOMAIN_MIPI] = {
+ .genpd = {
+ .name = "mipi",
+ },
+ .bits = {
+ .pxx = IMX8MN_MIPI_SW_Pxx_REQ,
+ .map = IMX8MN_MIPI_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MN_PGC_MIPI),
+ },
};
static const struct regmap_range imx8mn_yes_ranges[] = {
--
2.25.1
Add the DT binding for the i.MX8MN DISP blk-ctrl.
Signed-off-by: Adam Ford <[email protected]>
---
.../soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 97 +++++++++++++++++++
1 file changed, 97 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
new file mode 100644
index 000000000000..493b86658ad8
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MN DISP blk-ctrl
+
+maintainers:
+ - Lucas Stach <[email protected]>
+
+description:
+ The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to
+ the NoC and ensuring proper power sequencing of the display and MIPI CSI
+ peripherals located in the DISP domain of the SoC.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx8mn-disp-blk-ctrl
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ power-domains:
+ minItems: 5
+ maxItems: 5
+
+ power-domain-names:
+ items:
+ - const: bus
+ - const: isi
+ - const: lcdif
+ - const: mipi-dsi
+ - const: mipi-csi
+
+ clocks:
+ minItems: 11
+ maxItems: 11
+
+ clock-names:
+ items:
+ - const: disp_axi
+ - const: disp_apb
+ - const: disp_axi_root
+ - const: disp_apb_root
+ - const: lcdif-axi
+ - const: lcdif-apb
+ - const: lcdif-pix
+ - const: dsi-pclk
+ - const: dsi-ref
+ - const: csi-aclk
+ - const: csi-pclk
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - power-domain-names
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mm-clock.h>
+ #include <dt-bindings/power/imx8mn-power.h>
+
+ disp_blk_ctl: blk_ctrl@32e28000 {
+ compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
+ reg = <0x32e28000 0x100>;
+ power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
+ <&pgc_dispmix>, <&pgc_mipi>,
+ <&pgc_mipi>;
+ power-domain-names = "bus", "isi", "lcdif", "mipi-dsi",
+ "mipi-csi";
+ clocks = <&clk IMX8MN_CLK_DISP_AXI>,
+ <&clk IMX8MN_CLK_DISP_APB>,
+ <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
+ <&clk IMX8MN_CLK_DSI_CORE>,
+ <&clk IMX8MN_CLK_DSI_PHY_REF>,
+ <&clk IMX8MN_CLK_CSI1_PHY_REF>,
+ <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
+ clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root",
+ "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
+ "dsi-ref", "csi-aclk", "csi-pclk";
+ #power-domain-cells = <1>;
+ };
--
2.25.1
This adds the defines for the power domains provided by the DISP
blk-ctrl.
Signed-off-by: Adam Ford <[email protected]>
---
include/dt-bindings/power/imx8mn-power.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/dt-bindings/power/imx8mn-power.h b/include/dt-bindings/power/imx8mn-power.h
index 102ee85a9b62..eedd0e581939 100644
--- a/include/dt-bindings/power/imx8mn-power.h
+++ b/include/dt-bindings/power/imx8mn-power.h
@@ -12,4 +12,9 @@
#define IMX8MN_POWER_DOMAIN_DISPMIX 3
#define IMX8MN_POWER_DOMAIN_MIPI 4
+#define IMX8MN_DISPBLK_PD_MIPI_DSI 0
+#define IMX8MN_DISPBLK_PD_MIPI_CSI 1
+#define IMX8MN_DISPBLK_PD_LCDIF 2
+#define IMX8MN_DISPBLK_PD_ISI 3
+
#endif
--
2.25.1
Add the DT node for the DISP blk-ctrl. With this in place the
display/mipi power domains should be functional.
Signed-off-by: Adam Ford <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 28 +++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 4e9d7099bb4f..6ac14903bcef 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1011,6 +1011,34 @@ aips4: bus@32c00000 {
#size-cells = <1>;
ranges;
+ disp_blk_ctrl: blk-ctrl@32e28000 {
+ compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
+ reg = <0x32e28000 0x100>;
+ power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
+ <&pgc_dispmix>, <&pgc_mipi>,
+ <&pgc_mipi>;
+ power-domain-names = "bus", "isi",
+ "lcdif", "mipi-dsi",
+ "mipi-csi";
+ clocks = <&clk IMX8MN_CLK_DISP_AXI>,
+ <&clk IMX8MN_CLK_DISP_APB>,
+ <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
+ <&clk IMX8MN_CLK_DSI_CORE>,
+ <&clk IMX8MN_CLK_DSI_PHY_REF>,
+ <&clk IMX8MN_CLK_CSI1_PHY_REF>,
+ <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
+ clock-names = "disp_axi", "disp_apb",
+ "disp_axi_root", "disp_apb_root",
+ "lcdif-axi", "lcdif-apb", "lcdif-pix",
+ "dsi-pclk", "dsi-ref",
+ "csi-aclk", "csi-pclk";
+ #power-domain-cells = <1>;
+ };
+
usbotg1: usb@32e40000 {
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
reg = <0x32e40000 0x200>;
--
2.25.1
This adds the description for the i.MX8MN disp blk-ctrl.
Signed-off-by: Adam Ford <[email protected]>
---
drivers/soc/imx/imx8m-blk-ctrl.c | 75 +++++++++++++++++++++++++++++++-
1 file changed, 74 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index e172d295c441..8d3bf7690383 100644
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -14,6 +14,7 @@
#include <linux/clk.h>
#include <dt-bindings/power/imx8mm-power.h>
+#include <dt-bindings/power/imx8mn-power.h>
#define BLK_SFT_RSTN 0x0
#define BLK_CLK_EN 0x4
@@ -498,6 +499,75 @@ static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = {
.num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data),
};
+
+static int imx8mn_disp_power_notifier(struct notifier_block *nb,
+ unsigned long action, void *data)
+{
+ struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+ power_nb);
+
+ if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+ return NOTIFY_OK;
+
+ /* Enable bus clock and deassert bus reset */
+ regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
+ regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
+
+ /*
+ * On power up we have no software backchannel to the GPC to
+ * wait for the ADB handshake to happen, so we just delay for a
+ * bit. On power down the GPC driver waits for the handshake.
+ */
+ if (action == GENPD_NOTIFY_ON)
+ udelay(5);
+
+
+ return NOTIFY_OK;
+}
+
+static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = {
+ [IMX8MN_DISPBLK_PD_MIPI_DSI] = {
+ .name = "dispblk-mipi-dsi",
+ .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
+ .num_clks = 2,
+ .gpc_name = "mipi-dsi",
+ .rst_mask = BIT(0) | BIT(1),
+ .clk_mask = BIT(0) | BIT(1),
+ },
+ [IMX8MN_DISPBLK_PD_MIPI_CSI] = {
+ .name = "dispblk-mipi-csi",
+ .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
+ .num_clks = 2,
+ .gpc_name = "mipi-csi",
+ .rst_mask = BIT(2) | BIT(3),
+ .clk_mask = BIT(2) | BIT(3),
+ },
+ [IMX8MN_DISPBLK_PD_LCDIF] = {
+ .name = "dispblk-lcdif",
+ .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
+ .num_clks = 3,
+ .gpc_name = "lcdif",
+ .rst_mask = BIT(4) | BIT(5),
+ .clk_mask = BIT(4) | BIT(5),
+ },
+ [IMX8MN_DISPBLK_PD_ISI] = {
+ .name = "dispblk-isi",
+ .clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root",
+ "disp_apb_root"},
+ .num_clks = 4,
+ .gpc_name = "isi",
+ .rst_mask = BIT(6) | BIT(7),
+ .clk_mask = BIT(6) | BIT(7),
+ },
+};
+
+static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
+ .max_reg = 0x84,
+ .power_notifier_fn = imx8mn_disp_power_notifier,
+ .domains = imx8mn_disp_blk_ctl_domain_data,
+ .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
+};
+
static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
{
.compatible = "fsl,imx8mm-vpu-blk-ctrl",
@@ -505,7 +575,10 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
}, {
.compatible = "fsl,imx8mm-disp-blk-ctrl",
.data = &imx8mm_disp_blk_ctl_dev_data
- } ,{
+ }, {
+ .compatible = "fsl,imx8mn-disp-blk-ctrl",
+ .data = &imx8mn_disp_blk_ctl_dev_data
+ }, {
/* Sentinel */
}
};
--
2.25.1
Now that we have support for the power domain controller on the i.MX8MN,
we can put the USB controller in the respective power domain to allow
it to power down the PHY when possible.
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index f5bafd9db673..4e9d7099bb4f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1021,6 +1021,7 @@ usbotg1: usb@32e40000 {
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
+ power-domains = <&pgc_otg1>;
status = "disabled";
};
--
2.25.1
Add the DT node for the GPC, including all the PGC power domains,
some of them are not fully functional yet, as they require interaction
with the blk-ctrls to properly power up/down the peripherals.
Signed-off-by: Adam Ford <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 49 +++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index da6c942fb7f9..f5bafd9db673 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -4,6 +4,8 @@
*/
#include <dt-bindings/clock/imx8mn-clock.h>
+#include <dt-bindings/power/imx8mn-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -612,6 +614,53 @@ src: reset-controller@30390000 {
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
+
+ gpc: gpc@303a0000 {
+ compatible = "fsl,imx8mn-gpc";
+ reg = <0x303a0000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pgc_hsiomix: power-domain@0 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
+ clocks = <&clk IMX8MN_CLK_USB_BUS>;
+ };
+
+ pgc_otg1: power-domain@1 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MN_POWER_DOMAIN_OTG1>;
+ power-domains = <&pgc_hsiomix>;
+ };
+
+ pgc_gpumix: power-domain@2 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
+ clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
+ <&clk IMX8MN_CLK_GPU_SHADER>,
+ <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
+ <&clk IMX8MN_CLK_GPU_AHB>;
+ resets = <&src IMX8MQ_RESET_GPU_RESET>;
+ };
+
+ pgc_dispmix: power-domain@3 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
+ clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+ };
+
+ pgc_mipi: power-domain@4 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MN_POWER_DOMAIN_MIPI>;
+ power-domains = <&pgc_dispmix>;
+ };
+ };
+ };
};
aips2: bus@30400000 {
--
2.25.1
The i.MX8M-Nano features a GC7000. The Etnaviv driver detects it as:
etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203
Signed-off-by: Adam Ford <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 25 +++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 6ac14903bcef..2aafc17d8aa3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1089,6 +1089,31 @@ gpmi: nand-controller@33002000 {
status = "disabled";
};
+ gpu: gpu@38000000 {
+ compatible = "vivante,gc";
+ reg = <0x38000000 0x8000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_GPU_AHB>,
+ <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
+ <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
+ <&clk IMX8MN_CLK_GPU_SHADER>;
+ clock-names = "reg", "bus", "core", "shader";
+ assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
+ <&clk IMX8MN_CLK_GPU_SHADER>,
+ <&clk IMX8MN_CLK_GPU_AXI>,
+ <&clk IMX8MN_CLK_GPU_AHB>,
+ <&clk IMX8MN_GPU_PLL>,
+ <&clk IMX8MN_CLK_GPU_CORE>,
+ <&clk IMX8MN_CLK_GPU_SHADER>;
+ assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
+ <&clk IMX8MN_GPU_PLL_OUT>,
+ <&clk IMX8MN_SYS_PLL1_800M>,
+ <&clk IMX8MN_SYS_PLL1_800M>;
+ assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>,
+ <400000000>, <400000000>;
+ power-domains = <&pgc_gpumix>;
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>,
--
2.25.1
On Sat, 09 Oct 2021 11:26:54 -0500, Adam Ford wrote:
> Add the DT binding for the i.MX8MN DISP blk-ctrl.
>
> Signed-off-by: Adam Ford <[email protected]>
> ---
> .../soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 97 +++++++++++++++++++
> 1 file changed, 97 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.example.dts:30.26-27 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:385: Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1441: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1538808
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Sat, Oct 9, 2021 at 11:27 AM Adam Ford <[email protected]> wrote:
>
> This adds the description for the i.MX8MN disp blk-ctrl.
>
> Signed-off-by: Adam Ford <[email protected]>
> ---
Does anyone from NXP have any feedback on this?
I tried to look at the ISI driver and power domain and understand it,
but it's not present in the 8mm, so I went off my best understanding
of the datasheet.
adam
> drivers/soc/imx/imx8m-blk-ctrl.c | 75 +++++++++++++++++++++++++++++++-
> 1 file changed, 74 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
> index e172d295c441..8d3bf7690383 100644
> --- a/drivers/soc/imx/imx8m-blk-ctrl.c
> +++ b/drivers/soc/imx/imx8m-blk-ctrl.c
> @@ -14,6 +14,7 @@
> #include <linux/clk.h>
>
> #include <dt-bindings/power/imx8mm-power.h>
> +#include <dt-bindings/power/imx8mn-power.h>
>
> #define BLK_SFT_RSTN 0x0
> #define BLK_CLK_EN 0x4
> @@ -498,6 +499,75 @@ static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = {
> .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data),
> };
>
> +
> +static int imx8mn_disp_power_notifier(struct notifier_block *nb,
> + unsigned long action, void *data)
> +{
> + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
> + power_nb);
> +
> + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
> + return NOTIFY_OK;
> +
> + /* Enable bus clock and deassert bus reset */
> + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
> + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
> +
> + /*
> + * On power up we have no software backchannel to the GPC to
> + * wait for the ADB handshake to happen, so we just delay for a
> + * bit. On power down the GPC driver waits for the handshake.
> + */
> + if (action == GENPD_NOTIFY_ON)
> + udelay(5);
> +
> +
> + return NOTIFY_OK;
> +}
> +
> +static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = {
> + [IMX8MN_DISPBLK_PD_MIPI_DSI] = {
> + .name = "dispblk-mipi-dsi",
> + .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
> + .num_clks = 2,
> + .gpc_name = "mipi-dsi",
> + .rst_mask = BIT(0) | BIT(1),
> + .clk_mask = BIT(0) | BIT(1),
> + },
> + [IMX8MN_DISPBLK_PD_MIPI_CSI] = {
> + .name = "dispblk-mipi-csi",
> + .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
> + .num_clks = 2,
> + .gpc_name = "mipi-csi",
> + .rst_mask = BIT(2) | BIT(3),
> + .clk_mask = BIT(2) | BIT(3),
> + },
> + [IMX8MN_DISPBLK_PD_LCDIF] = {
> + .name = "dispblk-lcdif",
> + .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
> + .num_clks = 3,
> + .gpc_name = "lcdif",
> + .rst_mask = BIT(4) | BIT(5),
> + .clk_mask = BIT(4) | BIT(5),
> + },
> + [IMX8MN_DISPBLK_PD_ISI] = {
> + .name = "dispblk-isi",
> + .clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root",
> + "disp_apb_root"},
> + .num_clks = 4,
> + .gpc_name = "isi",
> + .rst_mask = BIT(6) | BIT(7),
> + .clk_mask = BIT(6) | BIT(7),
> + },
> +};
> +
> +static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
> + .max_reg = 0x84,
> + .power_notifier_fn = imx8mn_disp_power_notifier,
> + .domains = imx8mn_disp_blk_ctl_domain_data,
> + .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
> +};
> +
> static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
> {
> .compatible = "fsl,imx8mm-vpu-blk-ctrl",
> @@ -505,7 +575,10 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
> }, {
> .compatible = "fsl,imx8mm-disp-blk-ctrl",
> .data = &imx8mm_disp_blk_ctl_dev_data
> - } ,{
> + }, {
> + .compatible = "fsl,imx8mn-disp-blk-ctrl",
> + .data = &imx8mn_disp_blk_ctl_dev_data
> + }, {
> /* Sentinel */
> }
> };
> --
> 2.25.1
>
On Sat, Oct 9, 2021 at 11:27 AM Adam Ford <[email protected]> wrote:
>
> The blk-ctrl and the GPCv2 in the i.MX8MN is similar but slightly different to that
> of the i.MX8MM. This series is based on work from Lucas Stach for i.MX8MM, but
> adapted for i.MX8MN. With the additional power domains and blk-ctrl enabled,
> additional peripherals like gpu and USB can be enabled.
>
> V2: Add mising patches for expanding GPCv2 which are necessary
> to make the blk-ctl operate.
> Fix clk names
> Fix missing references to structures in blk-ctl driver to link
> them to the device tree.
>
I know Rob had some feedback on the DT bindings updates. I can
address them in V3, I was hoping to get some feedback from this series
from others who may be interested.
I don't know if it's too late to get this into 5.16 or not, but I'll
submit a V3 this weekend.
adam
> Adam Ford (9):
> soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled
> soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn
> dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains
> dt-bindings: soc: add binding for i.MX8MN DISP blk-ctrl
> soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl
> arm64: dts: imx8mn: add GPC node
> arm64: dts: imx8mn: put USB controller into power-domains
> arm64: dts: imx8mn: add DISP blk-ctrl
> arm64: dts: imx8mn: Enable GPU
>
> .../soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 97 +++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 103 ++++++++++++++++++
> drivers/soc/imx/gpcv2.c | 26 +++++
> drivers/soc/imx/imx8m-blk-ctrl.c | 75 ++++++++++++-
> include/dt-bindings/power/imx8mn-power.h | 5 +
> 5 files changed, 305 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
>
> --
> 2.25.1
>