The gpa1-4 pin was put twice in UART3 pin configuration of Exynos5250,
instead of proper pin gpa1-5.
Fixes: f8bfe2b050f3 ("ARM: dts: add pin state information in client nodes for Exynos5 platforms")
Cc: <[email protected]>
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index d31a68672bfa..d7d756614edd 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -260,7 +260,7 @@ i2c3_hs_bus: i2c3-hs-bus {
};
uart3_data: uart3-data {
- samsung,pins = "gpa1-4", "gpa1-4";
+ samsung,pins = "gpa1-4", "gpa1-5";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
--
2.32.0
Each pin configuration in pin controller should be a node with
"samsung,pins" and other similar properties. However the macro PIN()
(used for initial/sleep states) defines entire node, so PCIe WLAN pin
configuration node was ignored.
Fixes: 98c03b6eef3f ("arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards")
Cc: <[email protected]>
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index cbcc01a66aab..c5054c7a9c03 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -1104,8 +1104,11 @@ &pinctrl_ese {
pinctrl-names = "default";
pinctrl-0 = <&initial_ese>;
- pcie_wlanen: pcie-wlanen {
- PIN(INPUT, gpj2-0, UP, FAST_SR4);
+ pcie_wlanen: pcie-wlanen-pins {
+ samsung,pins = "gpj2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
};
initial_ese: initial-state {
--
2.32.0
The pin controller device node is expected to have one (optional)
interrupt. Its pin banks capable of external interrupts, should define
interrupts for each pin, unless a muxed interrupt is used.
Exynos850 defined the second part - interrupt for each pin in wake-up
pin controller - but also added these interrupts in main device node,
which is not correct.
Fixes: e3493220fd3e ("arm64: dts: exynos: Add initial Exynos850 SoC support")
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/exynos/exynos850.dtsi | 40 -----------------------
1 file changed, 40 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
index 2abbb972b610..4f0a40de5e67 100644
--- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
@@ -344,38 +344,6 @@ cmu_hsi: clock-controller@13400000 {
pinctrl_alive: pinctrl@11850000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x11850000 0x1000>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos7-wakeup-eint";
@@ -385,14 +353,6 @@ wakeup-interrupt-controller {
pinctrl_cmgp: pinctrl@11c30000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x11c30000 0x1000>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos7-wakeup-eint";
--
2.32.0
On 30/12/2021 20:53, Krzysztof Kozlowski wrote:
> Each pin configuration in pin controller should be a node with
> "samsung,pins" and other similar properties. However the macro PIN()
> (used for initial/sleep states) defines entire node, so PCIe WLAN pin
> configuration node was ignored.
>
> Fixes: 98c03b6eef3f ("arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards")
> Cc: <[email protected]>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
This patch is not correct, because the driver/bindings allow and work
with such DTS. Please ignore.
Best regards,
Krzysztof
On Thu, 30 Dec 2021 at 21:53, Krzysztof Kozlowski
<[email protected]> wrote:
>
> The pin controller device node is expected to have one (optional)
> interrupt. Its pin banks capable of external interrupts, should define
> interrupts for each pin, unless a muxed interrupt is used.
>
> Exynos850 defined the second part - interrupt for each pin in wake-up
> pin controller - but also added these interrupts in main device node,
> which is not correct.
>
> Fixes: e3493220fd3e ("arm64: dts: exynos: Add initial Exynos850 SoC support")
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
Tested-by: Sam Protsenko <[email protected]>
Reviewed-by: Sam Protsenko <[email protected]>
Despite some errors brought by this change:
samsung-pinctrl 11850000.pinctrl: irq number not available
samsung-pinctrl 11c30000.pinctrl: irq number not available
the interrupts seem to be functional still. Tested on E850-96 board,
by pressing buttons connected to gpa0..gpa1, and checking
/proc/interrupts info. I guess it's ok to merge this one as is, and
then work further to fix the driver (or dts?) accordingly.
Also, I submitted related patch ("arm64: dts: exynos: Add missing gpm6
and gpm7 nodes to Exynos850"), please take a look.
> arch/arm64/boot/dts/exynos/exynos850.dtsi | 40 -----------------------
> 1 file changed, 40 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
> index 2abbb972b610..4f0a40de5e67 100644
> --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
> @@ -344,38 +344,6 @@ cmu_hsi: clock-controller@13400000 {
> pinctrl_alive: pinctrl@11850000 {
> compatible = "samsung,exynos850-pinctrl";
> reg = <0x11850000 0x1000>;
> - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>
> wakeup-interrupt-controller {
> compatible = "samsung,exynos7-wakeup-eint";
> @@ -385,14 +353,6 @@ wakeup-interrupt-controller {
> pinctrl_cmgp: pinctrl@11c30000 {
> compatible = "samsung,exynos850-pinctrl";
> reg = <0x11c30000 0x1000>;
> - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
>
> wakeup-interrupt-controller {
> compatible = "samsung,exynos7-wakeup-eint";
> --
> 2.32.0
>
Hi Krzysztof
On Fri, Dec 31, 2021 at 4:02 PM Krzysztof Kozlowski
<[email protected]> wrote:
>
> The gpa1-4 pin was put twice in UART3 pin configuration of Exynos5250,
> instead of proper pin gpa1-5.
>
> Fixes: f8bfe2b050f3 ("ARM: dts: add pin state information in client nodes for Exynos5 platforms")
> Cc: <[email protected]>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
Thanks for fixing this.
Reviewed-by: Alim Akhtar <[email protected]>
> arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
> index d31a68672bfa..d7d756614edd 100644
> --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
> @@ -260,7 +260,7 @@ i2c3_hs_bus: i2c3-hs-bus {
> };
>
> uart3_data: uart3-data {
> - samsung,pins = "gpa1-4", "gpa1-4";
> + samsung,pins = "gpa1-4", "gpa1-5";
> samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
> --
> 2.32.0
>
--
Regards,
Alim
On 03/01/2022 22:09, Sam Protsenko wrote:
> On Thu, 30 Dec 2021 at 21:53, Krzysztof Kozlowski
> <[email protected]> wrote:
>>
>> The pin controller device node is expected to have one (optional)
>> interrupt. Its pin banks capable of external interrupts, should define
>> interrupts for each pin, unless a muxed interrupt is used.
>>
>> Exynos850 defined the second part - interrupt for each pin in wake-up
>> pin controller - but also added these interrupts in main device node,
>> which is not correct.
>>
>> Fixes: e3493220fd3e ("arm64: dts: exynos: Add initial Exynos850 SoC support")
>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>> ---
>
> Tested-by: Sam Protsenko <[email protected]>
> Reviewed-by: Sam Protsenko <[email protected]>
>
> Despite some errors brought by this change:
>
> samsung-pinctrl 11850000.pinctrl: irq number not available
> samsung-pinctrl 11c30000.pinctrl: irq number not available
>
> the interrupts seem to be functional still. Tested on E850-96 board,
> by pressing buttons connected to gpa0..gpa1, and checking
> /proc/interrupts info. I guess it's ok to merge this one as is, and
> then work further to fix the driver (or dts?) accordingly.
>
> Also, I submitted related patch ("arm64: dts: exynos: Add missing gpm6
> and gpm7 nodes to Exynos850"), please take a look.
>
Several Exynos850 pinctrl banks use exynos_eint_gpio_init, so they need
the interrupt property (for external interrupts). Otherwise external
GPIO interrupts won't work. The ones you checked, could be the external
wakeup interrupts which are not affected here.
This change seems wrong. Instead one interrupt should be left. However I
don't know which - should be described in reference manual in interrupt
sources.
Best regards,
Krzysztof
On 30.12.2021 20:53, Krzysztof Kozlowski wrote:
> The gpa1-4 pin was put twice in UART3 pin configuration of Exynos5250,
> instead of proper pin gpa1-5.
>
> Fixes: f8bfe2b050f3 ("ARM: dts: add pin state information in client nodes for Exynos5 platforms")
> Cc: <[email protected]>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
Well, the uart3_data node is not referenced anywhere, so this change is
not really relevant to any board, but for the completeness, feel free to
add:
Tested-by: Marek Szyprowski <[email protected]>
> ---
> arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
> index d31a68672bfa..d7d756614edd 100644
> --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
> @@ -260,7 +260,7 @@ i2c3_hs_bus: i2c3-hs-bus {
> };
>
> uart3_data: uart3-data {
> - samsung,pins = "gpa1-4", "gpa1-4";
> + samsung,pins = "gpa1-4", "gpa1-5";
> samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
On Thu, 30 Dec 2021 20:53:23 +0100, Krzysztof Kozlowski wrote:
> The gpa1-4 pin was put twice in UART3 pin configuration of Exynos5250,
> instead of proper pin gpa1-5.
>
>
Applied, thanks!
[1/3] ARM: dts: exynos: fix UART3 pins configuration in Exynos5250
commit: 372d7027fed43c8570018e124cf78b89523a1f8e
Best regards,
--
Krzysztof Kozlowski <[email protected]>
On Thu, 30 Dec 2021 20:53:25 +0100, Krzysztof Kozlowski wrote:
> The pin controller device node is expected to have one (optional)
> interrupt. Its pin banks capable of external interrupts, should define
> interrupts for each pin, unless a muxed interrupt is used.
>
> Exynos850 defined the second part - interrupt for each pin in wake-up
> pin controller - but also added these interrupts in main device node,
> which is not correct.
>
> [...]
Applied, thanks!
[3/3] arm64: dts: exynos: drop incorrectly placed wakeup interrupts in Exynos850
commit: daeb1c2b50fb98118d6318b5fdbd9ef9bdfaeaf5
Best regards,
--
Krzysztof Kozlowski <[email protected]>