This patch series adds a CCU driver for the RTC in the H616, R329 and
D1. The extra patch at the end of this series shows how it would be
explanded to additional hardware variants.
The driver is intended to support the existing binding used for the H6,
but also an updated binding which includes all RTC input clocks.
A future patch series could add functionality to the driver to manage
IOSC calibration at boot and during suspend/resume.
It may be possible to support all of these hardware variants without
adding this new driver, by adding them to the existing RTC clock
provider, but I'm concerned about the complexity there, without any of
the CCU abstraction.
Changes in v3:
- Add/fix several maxItems attributes for clocks and clock-items
- Drop the SUNXI_CCU_MUX_HW_WITH_KEY macro, since it is no longer used.
- Also drop the patch adding the SUNXI_CCU_MUX_DATA_WITH_GATE macro.
- Rebase on v5.17-rc2 (CCU module support series was merged).
- Move IOSC calibration control to prepare/unprepare operations.
- Declare several `struct clk_init_data`s as static variables (instead
of as anonymous) so they can be modified from the probe function
without casting away const.
- Instead of creating two copies of clocks which may or may not have
muxes, change the number of parents to 1 in the non-mux case.
- Use a single CCU description for all variants.
- Use IS_REACHABLE to guard the call to sun6i_rtc_ccu_probe.
- Allow the driver to be built on !ARM64 (i.e. RISCV).
- Rebase example on top of driver changes, and drop the second example.
Changes in v2:
- Combine "const"s to "enum" in the DT binding compatible property.
- Properly update the DT binding clocks and clock-names properties.
- Rebase on v2 of the CCU module support series.
- Load the CCU driver from the RTC driver, not as an OF provider.
Samuel Holland (6):
dt-bindings: rtc: sun6i: Clean up repetition
dt-bindings: rtc: sun6i: Add H616, R329, and D1 support
rtc: sun6i: Enable the bus clock when provided
clk: sunxi-ng: mux: Allow muxes to have keys
clk: sunxi-ng: Add support for the sun6i RTC clocks
[DO NOT MERGE] clk: sunxi-ng: sun6i-rtc: Add support for H6
.../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 84 +++-
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile | 2 +
drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 393 ++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun6i-rtc.h | 15 +
drivers/clk/sunxi-ng/ccu_common.h | 1 +
drivers/clk/sunxi-ng/ccu_mux.c | 7 +
drivers/rtc/rtc-sun6i.c | 48 ++-
include/dt-bindings/clock/sun6i-rtc.h | 10 +
include/linux/clk/sunxi-ng.h | 2 +
10 files changed, 538 insertions(+), 29 deletions(-)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-rtc.h
create mode 100644 include/dt-bindings/clock/sun6i-rtc.h
--
2.33.1
H6 supports IOSC calibration and an ext-osc32k input. Unlike newer SoCs,
it has a single parent for its fanout clock.
Add support for H6 in the CCU driver, replacing the support in the
existing early OF clock provider.
Signed-off-by: Samuel Holland <[email protected]>
---
Changes in v3:
- Rebase example on top of driver changes, and drop the second example.
drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 15 +++++++++++++++
drivers/rtc/rtc-sun6i.c | 17 -----------------
2 files changed, 15 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
index a39670a7c446..712fda22efd5 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
@@ -295,6 +295,10 @@ static const struct sunxi_ccu_desc sun6i_rtc_ccu_desc = {
.hw_clks = &sun6i_rtc_ccu_hw_clks,
};
+static const struct clk_parent_data sun50i_h6_osc32k_fanout_parents[] = {
+ { .hw = &osc32k_clk.common.hw },
+};
+
static const struct clk_parent_data sun50i_h616_osc32k_fanout_parents[] = {
{ .hw = &osc32k_clk.common.hw },
{ .fw_name = "pll-32k" },
@@ -307,6 +311,13 @@ static const struct clk_parent_data sun50i_r329_osc32k_fanout_parents[] = {
{ .hw = &osc24M_32k_clk.common.hw }
};
+static const struct sun6i_rtc_match_data sun50i_h6_rtc_ccu_data = {
+ .have_ext_osc32k = true,
+ .have_iosc_calibration = true,
+ .osc32k_fanout_parents = sun50i_h6_osc32k_fanout_parents,
+ .osc32k_fanout_nparents = ARRAY_SIZE(sun50i_h6_osc32k_fanout_parents),
+};
+
static const struct sun6i_rtc_match_data sun50i_h616_rtc_ccu_data = {
.have_iosc_calibration = true,
.rtc_32k_single_parent = true,
@@ -321,6 +332,10 @@ static const struct sun6i_rtc_match_data sun50i_r329_rtc_ccu_data = {
};
static const struct of_device_id sun6i_rtc_ccu_match[] = {
+ {
+ .compatible = "allwinner,sun50i-h6-rtc",
+ .data = &sun50i_h6_rtc_ccu_data,
+ },
{
.compatible = "allwinner,sun50i-h616-rtc",
.data = &sun50i_h616_rtc_ccu_data,
diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
index 35b34d14a1db..1a875a32357d 100644
--- a/drivers/rtc/rtc-sun6i.c
+++ b/drivers/rtc/rtc-sun6i.c
@@ -364,23 +364,6 @@ CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc",
CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc",
sun8i_h3_rtc_clk_init);
-static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = {
- .rc_osc_rate = 16000000,
- .fixed_prescaler = 32,
- .has_prescaler = 1,
- .has_out_clk = 1,
- .export_iosc = 1,
- .has_losc_en = 1,
- .has_auto_swt = 1,
-};
-
-static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
-{
- sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data);
-}
-CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
- sun50i_h6_rtc_clk_init);
-
/*
* The R40 user manual is self-conflicting on whether the prescaler is
* fixed or configurable. The clock diagram shows it as fixed, but there
--
2.33.1
The RTC power domain in sun6i and newer SoCs manages the 16 MHz RC
oscillator (called "IOSC" or "osc16M") and the optional 32 kHz crystal
oscillator (called "LOSC" or "osc32k"). Starting with the H6, this power
domain also handles the 24 MHz DCXO (called variously "HOSC", "dcxo24M",
or "osc24M") as well. The H6 also adds a calibration circuit for IOSC.
Later SoCs introduce further variations on the design:
- H616 adds an additional mux for the 32 kHz fanout source.
- R329 adds an additional mux for the RTC timekeeping clock, a clock
for the SPI bus between power domains inside the RTC, and removes the
IOSC calibration functionality.
Take advantage of the CCU framework to handle this increased complexity.
This driver is intended to be a drop-in replacement for the existing RTC
clock provider. So some runtime adjustment of the clock parents is
needed, both to handle hardware differences, and to support the old
binding which omitted some of the input clocks.
Signed-off-by: Samuel Holland <[email protected]>
---
Changes in v3:
- Rebase on v5.17-rc2 (CCU module support series was merged).
- Move IOSC calibration control to prepare/unprepare operations.
- Declare several `struct clk_init_data`s as static variables (instead
of as anonymous) so they can be modified from the probe function
without casting away const.
- Instead of creating two copies of clocks which may or may not have
muxes, change the number of parents to 1 in the non-mux case.
- Use a single CCU description for all variants.
- Use IS_REACHABLE to guard the call to sun6i_rtc_ccu_probe.
- Allow the driver to be built on !ARM64 (i.e. RISCV).
Changes in v2:
- Rebase on v2 of the CCU module support series.
- Load the CCU driver from the RTC driver, not as an OF provider.
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile | 2 +
drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 378 +++++++++++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun6i-rtc.h | 15 ++
drivers/rtc/rtc-sun6i.c | 7 +
include/linux/clk/sunxi-ng.h | 2 +
6 files changed, 409 insertions(+)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-rtc.h
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 68a94e5af8ed..461537679c04 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -69,6 +69,11 @@ config SUN6I_A31_CCU
default MACH_SUN6I
depends on MACH_SUN6I || COMPILE_TEST
+config SUN6I_RTC_CCU
+ tristate "Support for the Allwinner H616/R329 RTC CCU"
+ default ARCH_SUNXI
+ depends on ARCH_SUNXI || COMPILE_TEST
+
config SUN8I_A23_CCU
tristate "Support for the Allwinner A23 CCU"
default MACH_SUN8I
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index ec931cb7aa14..6b3ae2b620db 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o
obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o
obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o
obj-$(CONFIG_SUN6I_A31_CCU) += sun6i-a31-ccu.o
+obj-$(CONFIG_SUN6I_RTC_CCU) += sun6i-rtc-ccu.o
obj-$(CONFIG_SUN8I_A23_CCU) += sun8i-a23-ccu.o
obj-$(CONFIG_SUN8I_A33_CCU) += sun8i-a33-ccu.o
obj-$(CONFIG_SUN8I_A83T_CCU) += sun8i-a83t-ccu.o
@@ -60,6 +61,7 @@ sun50i-h616-ccu-y += ccu-sun50i-h616.o
sun4i-a10-ccu-y += ccu-sun4i-a10.o
sun5i-ccu-y += ccu-sun5i.o
sun6i-a31-ccu-y += ccu-sun6i-a31.o
+sun6i-rtc-ccu-y += ccu-sun6i-rtc.o
sun8i-a23-ccu-y += ccu-sun8i-a23.o
sun8i-a33-ccu-y += ccu-sun8i-a33.o
sun8i-a83t-ccu-y += ccu-sun8i-a83t.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
new file mode 100644
index 000000000000..a39670a7c446
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
@@ -0,0 +1,378 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2021 Samuel Holland <[email protected]>
+//
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+
+#include "ccu_common.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mux.h"
+
+#include "ccu-sun6i-rtc.h"
+
+#define IOSC_ACCURACY 300000000 /* 30% */
+#define IOSC_RATE 16000000
+
+#define LOSC_RATE 32768
+#define LOSC_RATE_SHIFT 15
+
+#define LOSC_CTRL_REG 0x0
+#define LOSC_CTRL_KEY 0x16aa0000
+
+#define IOSC_32K_CLK_DIV_REG 0x8
+#define IOSC_32K_CLK_DIV GENMASK(4, 0)
+#define IOSC_32K_PRE_DIV 32
+
+#define IOSC_CLK_CALI_REG 0xc
+#define IOSC_CLK_CALI_DIV_ONES 22
+#define IOSC_CLK_CALI_EN BIT(1)
+#define IOSC_CLK_CALI_SRC_SEL BIT(0)
+
+#define LOSC_OUT_GATING_REG 0x60
+
+#define DCXO_CTRL_REG 0x160
+#define DCXO_CTRL_CLK16M_RC_EN BIT(0)
+
+struct sun6i_rtc_match_data {
+ bool have_ext_osc32k : 1;
+ bool have_iosc_calibration : 1;
+ bool rtc_32k_single_parent : 1;
+ const struct clk_parent_data *osc32k_fanout_parents;
+ u8 osc32k_fanout_nparents;
+};
+
+static bool have_iosc_calibration;
+
+static int ccu_iosc_enable(struct clk_hw *hw)
+{
+ struct ccu_common *cm = hw_to_ccu_common(hw);
+
+ return ccu_gate_helper_enable(cm, DCXO_CTRL_CLK16M_RC_EN);
+}
+
+static void ccu_iosc_disable(struct clk_hw *hw)
+{
+ struct ccu_common *cm = hw_to_ccu_common(hw);
+
+ return ccu_gate_helper_disable(cm, DCXO_CTRL_CLK16M_RC_EN);
+}
+
+static int ccu_iosc_is_enabled(struct clk_hw *hw)
+{
+ struct ccu_common *cm = hw_to_ccu_common(hw);
+
+ return ccu_gate_helper_is_enabled(cm, DCXO_CTRL_CLK16M_RC_EN);
+}
+
+static unsigned long ccu_iosc_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct ccu_common *cm = hw_to_ccu_common(hw);
+
+ if (have_iosc_calibration) {
+ u32 reg = readl(cm->base + IOSC_CLK_CALI_REG);
+
+ /*
+ * Recover the IOSC frequency by shifting the ones place of
+ * (fixed-point divider * 32768) into bit zero.
+ */
+ if (reg & IOSC_CLK_CALI_EN)
+ return reg >> (IOSC_CLK_CALI_DIV_ONES - LOSC_RATE_SHIFT);
+ }
+
+ return IOSC_RATE;
+}
+
+static unsigned long ccu_iosc_recalc_accuracy(struct clk_hw *hw,
+ unsigned long parent_accuracy)
+{
+ return IOSC_ACCURACY;
+}
+
+static const struct clk_ops ccu_iosc_ops = {
+ .enable = ccu_iosc_enable,
+ .disable = ccu_iosc_disable,
+ .is_enabled = ccu_iosc_is_enabled,
+ .recalc_rate = ccu_iosc_recalc_rate,
+ .recalc_accuracy = ccu_iosc_recalc_accuracy,
+};
+
+static struct ccu_common iosc_clk = {
+ .reg = DCXO_CTRL_REG,
+ .hw.init = CLK_HW_INIT_NO_PARENT("iosc", &ccu_iosc_ops,
+ CLK_GET_RATE_NOCACHE),
+};
+
+static int ccu_iosc_32k_prepare(struct clk_hw *hw)
+{
+ struct ccu_common *cm = hw_to_ccu_common(hw);
+ u32 val;
+
+ if (!have_iosc_calibration)
+ return 0;
+
+ val = readl(cm->base + IOSC_CLK_CALI_REG);
+ writel(val | IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL,
+ cm->base + IOSC_CLK_CALI_REG);
+
+ return 0;
+}
+
+static void ccu_iosc_32k_unprepare(struct clk_hw *hw)
+{
+ struct ccu_common *cm = hw_to_ccu_common(hw);
+ u32 val;
+
+ if (!have_iosc_calibration)
+ return;
+
+ val = readl(cm->base + IOSC_CLK_CALI_REG);
+ writel(val & ~(IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL),
+ cm->base + IOSC_CLK_CALI_REG);
+}
+
+static unsigned long ccu_iosc_32k_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct ccu_common *cm = hw_to_ccu_common(hw);
+ u32 val;
+
+ if (have_iosc_calibration) {
+ val = readl(cm->base + IOSC_CLK_CALI_REG);
+
+ /* Assume the calibrated 32k clock is accurate. */
+ if (val & IOSC_CLK_CALI_SRC_SEL)
+ return LOSC_RATE;
+ }
+
+ val = readl(cm->base + IOSC_32K_CLK_DIV_REG) & IOSC_32K_CLK_DIV;
+
+ return parent_rate / IOSC_32K_PRE_DIV / (val + 1);
+}
+
+static unsigned long ccu_iosc_32k_recalc_accuracy(struct clk_hw *hw,
+ unsigned long parent_accuracy)
+{
+ struct ccu_common *cm = hw_to_ccu_common(hw);
+ u32 val;
+
+ if (have_iosc_calibration) {
+ val = readl(cm->base + IOSC_CLK_CALI_REG);
+
+ /* Assume the calibrated 32k clock is accurate. */
+ if (val & IOSC_CLK_CALI_SRC_SEL)
+ return 0;
+ }
+
+ return parent_accuracy;
+}
+
+static const struct clk_ops ccu_iosc_32k_ops = {
+ .prepare = ccu_iosc_32k_prepare,
+ .unprepare = ccu_iosc_32k_unprepare,
+ .recalc_rate = ccu_iosc_32k_recalc_rate,
+ .recalc_accuracy = ccu_iosc_32k_recalc_accuracy,
+};
+
+static struct ccu_common iosc_32k_clk = {
+ .hw.init = CLK_HW_INIT_HW("iosc-32k", &iosc_clk.hw,
+ &ccu_iosc_32k_ops,
+ CLK_GET_RATE_NOCACHE),
+};
+
+static const struct clk_hw *ext_osc32k[] = { NULL }; /* updated during probe */
+
+static SUNXI_CCU_GATE_HWS(ext_osc32k_gate_clk, "ext-osc32k-gate",
+ ext_osc32k, 0x0, BIT(4), 0);
+
+static const struct clk_hw *osc32k_parents[] = {
+ &iosc_32k_clk.hw,
+ &ext_osc32k_gate_clk.common.hw
+};
+
+static struct clk_init_data osc32k_init_data = {
+ .name = "osc32k",
+ .ops = &ccu_mux_ops,
+ .parent_hws = osc32k_parents,
+ .num_parents = ARRAY_SIZE(osc32k_parents), /* updated during probe */
+};
+
+static struct ccu_mux osc32k_clk = {
+ .mux = _SUNXI_CCU_MUX(0, 1),
+ .common = {
+ .reg = LOSC_CTRL_REG,
+ .features = CCU_FEATURE_KEY_FIELD,
+ .hw.init = &osc32k_init_data,
+ },
+};
+
+/* This falls back to the global name for fwnodes without a named reference. */
+static const struct clk_parent_data osc24M[] = {
+ { .fw_name = "hosc", .name = "osc24M" }
+};
+
+static struct ccu_gate osc24M_32k_clk = {
+ .enable = BIT(16),
+ .common = {
+ .reg = LOSC_OUT_GATING_REG,
+ .prediv = 750,
+ .features = CCU_FEATURE_ALL_PREDIV,
+ .hw.init = CLK_HW_INIT_PARENTS_DATA("osc24M-32k", osc24M,
+ &ccu_gate_ops, 0),
+ },
+};
+
+static const struct clk_hw *rtc_32k_parents[] = {
+ &osc32k_clk.common.hw,
+ &osc24M_32k_clk.common.hw
+};
+
+static struct clk_init_data rtc_32k_init_data = {
+ .name = "rtc-32k",
+ .ops = &ccu_mux_ops,
+ .parent_hws = rtc_32k_parents,
+ .num_parents = ARRAY_SIZE(rtc_32k_parents), /* updated during probe */
+};
+
+static struct ccu_mux rtc_32k_clk = {
+ .mux = _SUNXI_CCU_MUX(1, 1),
+ .common = {
+ .reg = LOSC_CTRL_REG,
+ .features = CCU_FEATURE_KEY_FIELD,
+ .hw.init = &rtc_32k_init_data,
+ },
+};
+
+static struct clk_init_data osc32k_fanout_init_data = {
+ .name = "osc32k-fanout",
+ .ops = &ccu_mux_ops,
+ /* parents are set during probe */
+};
+
+static struct ccu_mux osc32k_fanout_clk = {
+ .enable = BIT(0),
+ .mux = _SUNXI_CCU_MUX(1, 2),
+ .common = {
+ .reg = LOSC_OUT_GATING_REG,
+ .hw.init = &osc32k_fanout_init_data,
+ },
+};
+
+static struct ccu_common *sun6i_rtc_ccu_clks[] = {
+ &iosc_clk,
+ &iosc_32k_clk,
+ &ext_osc32k_gate_clk.common,
+ &osc32k_clk.common,
+ &osc24M_32k_clk.common,
+ &rtc_32k_clk.common,
+ &osc32k_fanout_clk.common,
+};
+
+static struct clk_hw_onecell_data sun6i_rtc_ccu_hw_clks = {
+ .num = CLK_NUMBER,
+ .hws = {
+ [CLK_OSC32K] = &osc32k_clk.common.hw,
+ [CLK_OSC32K_FANOUT] = &osc32k_fanout_clk.common.hw,
+ [CLK_IOSC] = &iosc_clk.hw,
+ [CLK_IOSC_32K] = &iosc_32k_clk.hw,
+ [CLK_EXT_OSC32K_GATE] = &ext_osc32k_gate_clk.common.hw,
+ [CLK_OSC24M_32K] = &osc24M_32k_clk.common.hw,
+ [CLK_RTC_32K] = &rtc_32k_clk.common.hw,
+ },
+};
+
+static const struct sunxi_ccu_desc sun6i_rtc_ccu_desc = {
+ .ccu_clks = sun6i_rtc_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun6i_rtc_ccu_clks),
+
+ .hw_clks = &sun6i_rtc_ccu_hw_clks,
+};
+
+static const struct clk_parent_data sun50i_h616_osc32k_fanout_parents[] = {
+ { .hw = &osc32k_clk.common.hw },
+ { .fw_name = "pll-32k" },
+ { .hw = &osc24M_32k_clk.common.hw }
+};
+
+static const struct clk_parent_data sun50i_r329_osc32k_fanout_parents[] = {
+ { .hw = &osc32k_clk.common.hw },
+ { .hw = &ext_osc32k_gate_clk.common.hw },
+ { .hw = &osc24M_32k_clk.common.hw }
+};
+
+static const struct sun6i_rtc_match_data sun50i_h616_rtc_ccu_data = {
+ .have_iosc_calibration = true,
+ .rtc_32k_single_parent = true,
+ .osc32k_fanout_parents = sun50i_h616_osc32k_fanout_parents,
+ .osc32k_fanout_nparents = ARRAY_SIZE(sun50i_h616_osc32k_fanout_parents),
+};
+
+static const struct sun6i_rtc_match_data sun50i_r329_rtc_ccu_data = {
+ .have_ext_osc32k = true,
+ .osc32k_fanout_parents = sun50i_r329_osc32k_fanout_parents,
+ .osc32k_fanout_nparents = ARRAY_SIZE(sun50i_r329_osc32k_fanout_parents),
+};
+
+static const struct of_device_id sun6i_rtc_ccu_match[] = {
+ {
+ .compatible = "allwinner,sun50i-h616-rtc",
+ .data = &sun50i_h616_rtc_ccu_data,
+ },
+ {
+ .compatible = "allwinner,sun50i-r329-rtc",
+ .data = &sun50i_r329_rtc_ccu_data,
+ },
+};
+
+int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg)
+{
+ const struct sun6i_rtc_match_data *data;
+ struct clk *ext_osc32k_clk = NULL;
+ const struct of_device_id *match;
+
+ /* This driver is only used for newer variants of the hardware. */
+ match = of_match_device(sun6i_rtc_ccu_match, dev);
+ if (!match)
+ return 0;
+
+ data = match->data;
+ have_iosc_calibration = data->have_iosc_calibration;
+
+ if (data->have_ext_osc32k) {
+ const char *fw_name;
+
+ /* ext-osc32k was the only input clock in the old binding. */
+ fw_name = of_property_read_bool(dev->of_node, "clock-names")
+ ? "ext-osc32k" : NULL;
+ ext_osc32k_clk = devm_clk_get_optional(dev, fw_name);
+ if (IS_ERR(ext_osc32k_clk))
+ return PTR_ERR(ext_osc32k_clk);
+ }
+
+ if (ext_osc32k_clk) {
+ /* Link ext-osc32k-gate to its parent. */
+ *ext_osc32k = __clk_get_hw(ext_osc32k_clk);
+ } else {
+ /* ext-osc32k-gate is an orphan, so do not register it. */
+ sun6i_rtc_ccu_hw_clks.hws[CLK_EXT_OSC32K_GATE] = NULL;
+ osc32k_init_data.num_parents = 1;
+ }
+
+ if (data->rtc_32k_single_parent)
+ rtc_32k_init_data.num_parents = 1;
+
+ osc32k_fanout_init_data.parent_data = data->osc32k_fanout_parents;
+ osc32k_fanout_init_data.num_parents = data->osc32k_fanout_nparents;
+
+ return devm_sunxi_ccu_probe(dev, reg, &sun6i_rtc_ccu_desc);
+}
+
+MODULE_IMPORT_NS(SUNXI_CCU);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h
new file mode 100644
index 000000000000..9ae821fc2599
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _CCU_SUN6I_RTC_H
+#define _CCU_SUN6I_RTC_H
+
+#include <dt-bindings/clock/sun6i-rtc.h>
+
+#define CLK_IOSC_32K 3
+#define CLK_EXT_OSC32K_GATE 4
+#define CLK_OSC24M_32K 5
+#define CLK_RTC_32K 6
+
+#define CLK_NUMBER (CLK_RTC_32K + 1)
+
+#endif /* _CCU_SUN6I_RTC_H */
diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
index d5a86cbb2e94..35b34d14a1db 100644
--- a/drivers/rtc/rtc-sun6i.c
+++ b/drivers/rtc/rtc-sun6i.c
@@ -13,6 +13,7 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
+#include <linux/clk/sunxi-ng.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/fs.h>
@@ -707,6 +708,12 @@ static int sun6i_rtc_probe(struct platform_device *pdev)
chip->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(chip->base))
return PTR_ERR(chip->base);
+
+ if (IS_REACHABLE(CONFIG_SUN6I_RTC_CCU)) {
+ ret = sun6i_rtc_ccu_probe(dev, chip->base);
+ if (ret)
+ return ret;
+ }
}
platform_set_drvdata(pdev, chip);
diff --git a/include/linux/clk/sunxi-ng.h b/include/linux/clk/sunxi-ng.h
index cf32123b39f5..57c8ec44ab4e 100644
--- a/include/linux/clk/sunxi-ng.h
+++ b/include/linux/clk/sunxi-ng.h
@@ -9,4 +9,6 @@
int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode);
int sunxi_ccu_get_mmc_timing_mode(struct clk *clk);
+int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg);
+
#endif
--
2.33.1
The muxes in the RTC can only be updated when setting a key field to a
specific value. Add a feature flag to denote muxes with this property.
Since so far the key value is always the same, it does not need to be
provided separately for each mux.
Signed-off-by: Samuel Holland <[email protected]>
---
Changes in v3:
- Drop the SUNXI_CCU_MUX_HW_WITH_KEY macro, since it is no longer used.
drivers/clk/sunxi-ng/ccu_common.h | 1 +
drivers/clk/sunxi-ng/ccu_mux.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
index 98a1834b58bb..fbf16c6b896d 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -17,6 +17,7 @@
#define CCU_FEATURE_LOCK_REG BIT(5)
#define CCU_FEATURE_MMC_TIMING_SWITCH BIT(6)
#define CCU_FEATURE_SIGMA_DELTA_MOD BIT(7)
+#define CCU_FEATURE_KEY_FIELD BIT(8)
/* MMC timing mode switch bit */
#define CCU_MMC_NEW_TIMING_MODE BIT(30)
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index 2306a1cd83e4..1d557e323169 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -12,6 +12,8 @@
#include "ccu_gate.h"
#include "ccu_mux.h"
+#define CCU_MUX_KEY_VALUE 0x16aa0000
+
static u16 ccu_mux_get_prediv(struct ccu_common *common,
struct ccu_mux_internal *cm,
int parent_index)
@@ -191,6 +193,11 @@ int ccu_mux_helper_set_parent(struct ccu_common *common,
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + common->reg);
+
+ /* The key field always reads as zero. */
+ if (common->features & CCU_FEATURE_KEY_FIELD)
+ reg |= CCU_MUX_KEY_VALUE;
+
reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift);
writel(reg | (index << cm->shift), common->base + common->reg);
--
2.33.1
- Use "enum" for compatibles instead of several "const" alternatives.
- Merge the H6 clock-output-names minItems/maxItems constraint into the
identical block above.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
---
(no changes since v2)
Changes in v2:
- Combine "const"s to "enum" in the DT binding compatible property.
.../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 28 ++++++-------------
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
index beeb90e55727..a88d46ffb457 100644
--- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
@@ -16,16 +16,17 @@ properties:
compatible:
oneOf:
- - const: allwinner,sun6i-a31-rtc
- - const: allwinner,sun8i-a23-rtc
- - const: allwinner,sun8i-h3-rtc
- - const: allwinner,sun8i-r40-rtc
- - const: allwinner,sun8i-v3-rtc
- - const: allwinner,sun50i-h5-rtc
+ - enum:
+ - allwinner,sun6i-a31-rtc
+ - allwinner,sun8i-a23-rtc
+ - allwinner,sun8i-h3-rtc
+ - allwinner,sun8i-r40-rtc
+ - allwinner,sun8i-v3-rtc
+ - allwinner,sun50i-h5-rtc
+ - allwinner,sun50i-h6-rtc
- items:
- const: allwinner,sun50i-a64-rtc
- const: allwinner,sun8i-h3-rtc
- - const: allwinner,sun50i-h6-rtc
reg:
maxItems: 1
@@ -85,18 +86,7 @@ allOf:
enum:
- allwinner,sun8i-h3-rtc
- allwinner,sun50i-h5-rtc
-
- then:
- properties:
- clock-output-names:
- minItems: 3
- maxItems: 3
-
- - if:
- properties:
- compatible:
- contains:
- const: allwinner,sun50i-h6-rtc
+ - allwinner,sun50i-h6-rtc
then:
properties:
--
2.33.1
These new RTC variants all have a single alarm, like the R40 variant.
For the new SoCs, start requiring a complete list of input clocks. The
H616 has three required clocks. The R329 also has three required clocks
(but one is different), plus an optional crystal oscillator input. The
D1 RTC is identical to the one in the R329.
And since these new SoCs will have a well-defined output clock order as
well, they do not need the clock-output-names property.
Signed-off-by: Samuel Holland <[email protected]>
---
Changes in v3:
- Add/fix several maxItems attributes for clocks and clock-items
Changes in v2:
- Properly update the DT binding clocks and clock-names properties.
.../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 76 ++++++++++++++++++-
include/dt-bindings/clock/sun6i-rtc.h | 10 +++
2 files changed, 83 insertions(+), 3 deletions(-)
create mode 100644 include/dt-bindings/clock/sun6i-rtc.h
diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
index a88d46ffb457..0b767fec39d8 100644
--- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
@@ -24,9 +24,14 @@ properties:
- allwinner,sun8i-v3-rtc
- allwinner,sun50i-h5-rtc
- allwinner,sun50i-h6-rtc
+ - allwinner,sun50i-h616-rtc
+ - allwinner,sun50i-r329-rtc
- items:
- const: allwinner,sun50i-a64-rtc
- const: allwinner,sun8i-h3-rtc
+ - items:
+ - const: allwinner,sun20i-d1-rtc
+ - const: allwinner,sun50i-r329-rtc
reg:
maxItems: 1
@@ -38,7 +43,12 @@ properties:
- description: RTC Alarm 1
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
clock-output-names:
minItems: 1
@@ -98,7 +108,68 @@ allOf:
properties:
compatible:
contains:
- const: allwinner,sun8i-r40-rtc
+ const: allwinner,sun50i-h616-rtc
+
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ items:
+ - description: Bus clock for register access
+ - description: 24 MHz oscillator
+ - description: 32 kHz clock from the CCU
+
+ clock-names:
+ minItems: 3
+ maxItems: 3
+ items:
+ - const: bus
+ - const: hosc
+ - const: pll-32k
+
+ required:
+ - clocks
+ - clock-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun50i-r329-rtc
+
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 4
+ items:
+ - description: Bus clock for register access
+ - description: 24 MHz oscillator
+ - description: AHB parent for internal SPI clock
+ - description: External 32768 Hz oscillator
+
+ clock-names:
+ minItems: 3
+ maxItems: 4
+ items:
+ - const: bus
+ - const: hosc
+ - const: ahb
+ - const: ext-osc32k
+
+ required:
+ - clocks
+ - clock-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - allwinner,sun8i-r40-rtc
+ - allwinner,sun50i-h616-rtc
+ - allwinner,sun50i-r329-rtc
then:
properties:
@@ -117,7 +188,6 @@ required:
- compatible
- reg
- interrupts
- - clock-output-names
additionalProperties: false
diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h
new file mode 100644
index 000000000000..c845493e4d37
--- /dev/null
+++ b/include/dt-bindings/clock/sun6i-rtc.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+
+#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_
+#define _DT_BINDINGS_CLK_SUN6I_RTC_H_
+
+#define CLK_OSC32K 0
+#define CLK_OSC32K_FANOUT 1
+#define CLK_IOSC 2
+
+#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */
--
2.33.1
On Wed, 2 Feb 2022 20:17:35 -0600, Samuel Holland wrote:
> The RTC power domain in sun6i and newer SoCs manages the 16 MHz RC
> oscillator (called "IOSC" or "osc16M") and the optional 32 kHz crystal
> oscillator (called "LOSC" or "osc32k"). Starting with the H6, this power
> domain also handles the 24 MHz DCXO (called variously "HOSC", "dcxo24M",
> or "osc24M") as well. The H6 also adds a calibration circuit for IOSC.
>
> Later SoCs introduce further variations on the design:
> - H616 adds an additional mux for the 32 kHz fanout source.
> - R329 adds an additional mux for the RTC timekeeping clock, a clock
> for the SPI bus between power domains inside the RTC, and removes the
> IOSC calibration functionality.
>
> [...]
Applied to local tree (sunxi/clk-for-5.18).
Thanks!
Maxime
On Wed, 2 Feb 2022 20:17:34 -0600, Samuel Holland wrote:
> The muxes in the RTC can only be updated when setting a key field to a
> specific value. Add a feature flag to denote muxes with this property.
>
> Since so far the key value is always the same, it does not need to be
> provided separately for each mux.
>
>
> [...]
Applied to local tree (sunxi/clk-for-5.18).
Thanks!
Maxime
On Wed, Feb 02, 2022 at 08:17:32PM -0600, Samuel Holland wrote:
> These new RTC variants all have a single alarm, like the R40 variant.
>
> For the new SoCs, start requiring a complete list of input clocks. The
> H616 has three required clocks. The R329 also has three required clocks
> (but one is different), plus an optional crystal oscillator input. The
> D1 RTC is identical to the one in the R329.
>
> And since these new SoCs will have a well-defined output clock order as
> well, they do not need the clock-output-names property.
>
> Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Maxime Ripard <[email protected]>
Maxime
On Wed, 02 Feb 2022 20:17:32 -0600, Samuel Holland wrote:
> These new RTC variants all have a single alarm, like the R40 variant.
>
> For the new SoCs, start requiring a complete list of input clocks. The
> H616 has three required clocks. The R329 also has three required clocks
> (but one is different), plus an optional crystal oscillator input. The
> D1 RTC is identical to the one in the R329.
>
> And since these new SoCs will have a well-defined output clock order as
> well, they do not need the clock-output-names property.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> Changes in v3:
> - Add/fix several maxItems attributes for clocks and clock-items
>
> Changes in v2:
> - Properly update the DT binding clocks and clock-names properties.
>
> .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 76 ++++++++++++++++++-
> include/dt-bindings/clock/sun6i-rtc.h | 10 +++
> 2 files changed, 83 insertions(+), 3 deletions(-)
> create mode 100644 include/dt-bindings/clock/sun6i-rtc.h
>
Reviewed-by: Rob Herring <[email protected]>
Hi Maxime,
On 2/7/22 3:00 AM, Maxime Ripard wrote:
> On Wed, 2 Feb 2022 20:17:35 -0600, Samuel Holland wrote:
>> The RTC power domain in sun6i and newer SoCs manages the 16 MHz RC
>> oscillator (called "IOSC" or "osc16M") and the optional 32 kHz crystal
>> oscillator (called "LOSC" or "osc32k"). Starting with the H6, this power
>> domain also handles the 24 MHz DCXO (called variously "HOSC", "dcxo24M",
>> or "osc24M") as well. The H6 also adds a calibration circuit for IOSC.
>>
>> Later SoCs introduce further variations on the design:
>> - H616 adds an additional mux for the 32 kHz fanout source.
>> - R329 adds an additional mux for the RTC timekeeping clock, a clock
>> for the SPI bus between power domains inside the RTC, and removes the
>> IOSC calibration functionality.
>>
>> [...]
>
> Applied to local tree (sunxi/clk-for-5.18).
Part of the build failures were because this patch depends on patch 3. Is that
okay, or should I update this patch to be independent?
Regards,
Samuel
On Wed, Feb 02, 2022 at 08:17:31PM -0600, Samuel Holland wrote:
> - Use "enum" for compatibles instead of several "const" alternatives.
> - Merge the H6 clock-output-names minItems/maxItems constraint into the
> identical block above.
>
> Reviewed-by: Rob Herring <[email protected]>
> Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Maxime Ripard <[email protected]>
Maxime
Hi Samuel,
On Mon, Feb 07, 2022 at 05:54:02PM -0600, Samuel Holland wrote:
> On 2/7/22 3:00 AM, Maxime Ripard wrote:
> > On Wed, 2 Feb 2022 20:17:35 -0600, Samuel Holland wrote:
> >> The RTC power domain in sun6i and newer SoCs manages the 16 MHz RC
> >> oscillator (called "IOSC" or "osc16M") and the optional 32 kHz crystal
> >> oscillator (called "LOSC" or "osc32k"). Starting with the H6, this power
> >> domain also handles the 24 MHz DCXO (called variously "HOSC", "dcxo24M",
> >> or "osc24M") as well. The H6 also adds a calibration circuit for IOSC.
> >>
> >> Later SoCs introduce further variations on the design:
> >> - H616 adds an additional mux for the 32 kHz fanout source.
> >> - R329 adds an additional mux for the RTC timekeeping clock, a clock
> >> for the SPI bus between power domains inside the RTC, and removes the
> >> IOSC calibration functionality.
> >>
> >> [...]
> >
> > Applied to local tree (sunxi/clk-for-5.18).
>
> Part of the build failures were because this patch depends on patch 3. Is that
> okay, or should I update this patch to be independent?
We don't have anything queued up yet, so I think the easiest would be to
merge this through the RTC tree. So nothing to do on your side yet, we
just need Alex to answer :)
Maxime
Hello,
On 02/02/2022 20:17:30-0600, Samuel Holland wrote:
> This patch series adds a CCU driver for the RTC in the H616, R329 and
> D1. The extra patch at the end of this series shows how it would be
> explanded to additional hardware variants.
>
> The driver is intended to support the existing binding used for the H6,
> but also an updated binding which includes all RTC input clocks.
>
> A future patch series could add functionality to the driver to manage
> IOSC calibration at boot and during suspend/resume.
>
> It may be possible to support all of these hardware variants without
> adding this new driver, by adding them to the existing RTC clock
> provider, but I'm concerned about the complexity there, without any of
> the CCU abstraction.
>
> Changes in v3:
> - Add/fix several maxItems attributes for clocks and clock-items
> - Drop the SUNXI_CCU_MUX_HW_WITH_KEY macro, since it is no longer used.
> - Also drop the patch adding the SUNXI_CCU_MUX_DATA_WITH_GATE macro.
> - Rebase on v5.17-rc2 (CCU module support series was merged).
> - Move IOSC calibration control to prepare/unprepare operations.
> - Declare several `struct clk_init_data`s as static variables (instead
> of as anonymous) so they can be modified from the probe function
> without casting away const.
> - Instead of creating two copies of clocks which may or may not have
> muxes, change the number of parents to 1 in the non-mux case.
> - Use a single CCU description for all variants.
> - Use IS_REACHABLE to guard the call to sun6i_rtc_ccu_probe.
> - Allow the driver to be built on !ARM64 (i.e. RISCV).
> - Rebase example on top of driver changes, and drop the second example.
>
> Changes in v2:
> - Combine "const"s to "enum" in the DT binding compatible property.
> - Properly update the DT binding clocks and clock-names properties.
> - Rebase on v2 of the CCU module support series.
> - Load the CCU driver from the RTC driver, not as an OF provider.
>
> Samuel Holland (6):
> dt-bindings: rtc: sun6i: Clean up repetition
> dt-bindings: rtc: sun6i: Add H616, R329, and D1 support
> rtc: sun6i: Enable the bus clock when provided
I've now applied 1-3/6, thanks!
> clk: sunxi-ng: mux: Allow muxes to have keys
> clk: sunxi-ng: Add support for the sun6i RTC clocks
> [DO NOT MERGE] clk: sunxi-ng: sun6i-rtc: Add support for H6
>
> .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 84 +++-
> drivers/clk/sunxi-ng/Kconfig | 5 +
> drivers/clk/sunxi-ng/Makefile | 2 +
> drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 393 ++++++++++++++++++
> drivers/clk/sunxi-ng/ccu-sun6i-rtc.h | 15 +
> drivers/clk/sunxi-ng/ccu_common.h | 1 +
> drivers/clk/sunxi-ng/ccu_mux.c | 7 +
> drivers/rtc/rtc-sun6i.c | 48 ++-
> include/dt-bindings/clock/sun6i-rtc.h | 10 +
> include/linux/clk/sunxi-ng.h | 2 +
> 10 files changed, 538 insertions(+), 29 deletions(-)
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-rtc.h
> create mode 100644 include/dt-bindings/clock/sun6i-rtc.h
>
> --
> 2.33.1
>
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Wed, 2 Feb 2022 20:17:30 -0600, Samuel Holland wrote:
> This patch series adds a CCU driver for the RTC in the H616, R329 and
> D1. The extra patch at the end of this series shows how it would be
> explanded to additional hardware variants.
>
> The driver is intended to support the existing binding used for the H6,
> but also an updated binding which includes all RTC input clocks.
>
> [...]
Applied, thanks!
[1/6] dt-bindings: rtc: sun6i: Clean up repetition
(no commit info)
[2/6] dt-bindings: rtc: sun6i: Add H616, R329, and D1 support
(no commit info)
[3/6] rtc: sun6i: Enable the bus clock when provided
(no commit info)
[4/6] clk: sunxi-ng: mux: Allow muxes to have keys
commit: b6e649834afa1fc6fd856b287e808cebe2c6fb8e
[5/6] clk: sunxi-ng: Add support for the sun6i RTC clocks
commit: df8925adc02f1cb2c87582d688dd8991aaabf8b2
[6/6] clk: sunxi-ng: sun6i-rtc: Add support for H6
commit: dc1d63a697304fbd246e24901e0635885856ef63
Best regards,
--
Alexandre Belloni <[email protected]>