2022-02-08 22:27:13

by Srinivasa Rao Mandadapu

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Subject: [PATCH v2 0/3] Add lpass pin control support for audio on sc7280 based targets

This patch set is to add lpass pin control support for Audio over I2S,
wcd codec and digital mics.

This patch set depends on:
-- https://patchwork.kernel.org/project/alsa-devel/patch/[email protected]/

Changes Since V1:
-- Merge pinmux and pinconf properties in amp_en and wcd pin reset node.
-- Split common i2s pin control nodes to functionality specific nodes.
-- Move board specific properties to board specific dtsi file.
-- Update dmic pin control node name.

Srinivasa Rao Mandadapu (3):
arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset
arm64: dts: qcom: sc7280: add lpass lpi pin controller node
arm64: dts: qcom: sc7280: Add wcd9380 pinmux

arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 205 +++++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++
2 files changed, 245 insertions(+)

--
2.7.4



2022-02-09 09:53:16

by Srinivasa Rao Mandadapu

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Subject: [PATCH v2 1/3] arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset

Add AMP enable node and pinmux for primary and secondary I2S
for SC7280 based platforms.

Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 40 ++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++++++
2 files changed, 80 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index d623d71..c7d6c46 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -436,6 +436,39 @@
qcom,drive-strength = <3>;
};
};
+&pri_mi2s_data0 {
+ drive-strength = <6>;
+};
+
+&pri_mi2s_data1 {
+ drive-strength = <6>;
+};
+
+&pri_mi2s_mclk {
+ drive-strength = <6>;
+};
+
+&pri_mi2s_sclk {
+ drive-strength = <6>;
+};
+
+&pri_mi2s_ws {
+ drive-strength = <6>;
+};
+
+&sec_mi2s_data0 {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&sec_mi2s_sclk {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&sec_mi2s_ws {
+ drive-strength = <6>;
+};

&qspi_cs0 {
bias-disable;
@@ -491,6 +524,13 @@
};

&tlmm {
+ amp_en: amp-en {
+ pins = "gpio63";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
nvme_pwren: nvme-pwren {
function = "gpio";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 937c2e0..76e73e9 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3461,6 +3461,46 @@
};
};

+ pri_mi2s_data0: pri-mi2s-data0 {
+ pins = "gpio98";
+ function = "mi2s0_data0";
+ };
+
+ pri_mi2s_data1: pri-mi2s-data1 {
+ pins = "gpio99";
+ function = "mi2s0_data1";
+ };
+
+ pri_mi2s_mclk: pri-mi2s-mclk {
+ pins = "gpio96";
+ function = "pri_mi2s";
+ };
+
+ pri_mi2s_sclk: pri-mi2s-sclk {
+ pins = "gpio97";
+ function = "mi2s0_sck";
+ };
+
+ pri_mi2s_ws: pri-mi2s-ws {
+ pins = "gpio100";
+ function = "mi2s0_ws";
+ };
+
+ sec_mi2s_data0: sec-mi2s-data0 {
+ pins = "gpio107";
+ function = "mi2s1_data0";
+ };
+
+ sec_mi2s_sclk: sec-mi2s-sclk {
+ pins = "gpio106";
+ function = "mi2s1_sck";
+ };
+
+ sec_mi2s_ws: sec-mi2s-ws {
+ pins = "gpio108";
+ function = "mi2s1_ws";
+ };
+
qup_uart8_cts: qup-uart8-cts {
pins = "gpio32";
function = "qup10";
--
2.7.4


2022-02-09 12:20:03

by Srinivasa Rao Mandadapu

[permalink] [raw]
Subject: [PATCH v2 2/3] arm64: dts: qcom: sc7280: add lpass lpi pin controller node

Add LPASS LPI pinctrl node required for Audio functionality on sc7280
based platforms.

Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 150 +++++++++++++++++++++++++++++++
1 file changed, 150 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index c7d6c46..4704a93 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -638,3 +638,153 @@
bias-pull-up;
};
};
+&soc {
+ lpass_tlmm: pinctrl@33c0000 {
+ compatible = "qcom,sc7280-lpass-lpi-pinctrl";
+ reg = <0 0x33c0000 0x0 0x20000>,
+ <0 0x3550000 0x0 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 15>;
+
+ #clock-cells = <1>;
+
+ dmic01_active: dmic01-active-pins {
+ clk {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+ data {
+ pins = "gpio7";
+ function = "dmic1_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ dmic01_sleep: dmic01-sleep-pins {
+ clk {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+
+ data {
+ pins = "gpio7";
+ function = "dmic1_data";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+
+ dmic23_active: dmic02-active-pins {
+ clk {
+ pins = "gpio8";
+ function = "dmic2_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+ data {
+ pins = "gpio9";
+ function = "dmic2_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ dmic23_sleep: dmic02-sleep-pins {
+ clk {
+ pins = "gpio8";
+ function = "dmic2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+
+ data {
+ pins = "gpio9";
+ function = "dmic2_data";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+
+ rx_swr_active: rx_swr-active-pins {
+ clk {
+ pins = "gpio3";
+ function = "swr_rx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data {
+ pins = "gpio4", "gpio5";
+ function = "swr_rx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_sleep: rx_swr-sleep-pins {
+ clk {
+ pins = "gpio3";
+ function = "swr_rx_clk";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+
+ data {
+ pins = "gpio4", "gpio5";
+ function = "swr_rx_data";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ tx_swr_active: tx_swr-active-pins {
+ clk {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data {
+ pins = "gpio1", "gpio2", "gpio14";
+ function = "swr_tx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_sleep: tx_swr-sleep-pins {
+ clk {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+
+ data {
+ pins = "gpio1", "gpio2", "gpio14";
+ function = "swr_tx_data";
+ drive-strength = <2>;
+ input-enable;
+ bias-bus-hold;
+ };
+ };
+ };
+};
--
2.7.4