2022-02-09 07:11:03

by Kathiravan Thirumoorthy

Subject: [PATCH 0/2] Enable the GICv2m extension support for IPQ8074/IPQ6018

GIC used in the IPQ8074 and IPQ6018 family of SoCs has one instance of
GICv2m extension, which supports upto 32 MSI interrupts. This series
enables the support for the same.

Kathiravan T (2):
arm64: dts: qcom: ipq8074: enable the GICv2m support
arm64: dts: qcom: ipq6018: enable the GICv2m support

arch/arm64/boot/dts/qcom/ipq6018.dtsi | 9 +++++++++
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
2 files changed, 18 insertions(+)

--
2.7.4

2022-02-09 09:55:01

by Kathiravan Thirumoorthy

Subject: [PATCH 1/2] arm64: dts: qcom: ipq8074: enable the GICv2m support

GIC used in the IPQ8074 SoCs has one instance of the GICv2m extension,
which supports upto 32 MSI interrupts. Lets add support for the same.

Signed-off-by: Kathiravan T <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 26ba7ce9222c..7b0258407d10 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -620,9 +620,18 @@

intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
+ #address-cells = <1>;
+ #size-cells = <1>;
interrupt-controller;
#interrupt-cells = <0x3>;
reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
+ ranges = <0 0xb00a000 0xffd>;
+
+ v2m@0 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x0 0xffd>;
+ };
};

timer {
--
2.7.4