Based on the i.MX8MP GPC and blk-ctrl patch-set [1] issued by Lucas.
This series patches add the i.MX8MP PCIe support.
- i.MX8MP PCIe PHY has two resets refer to the i.MX8MM PCIe PHY.
Add one more PHY reset for i.MX8MP PCIe PHY accordingly.
- Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
And share as much as possible codes with i.MX8MM PCIe PHY.
- Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
driver.
Tested on the i.MX8MM EVK and i.MX8MP EVK boards, PCIe works fine.
[1]:https://patchwork.kernel.org/project/linux-arm-kernel/cover/[email protected]/
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 1 +
Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 4 +-
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 55 ++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46 ++++++++++++++-
drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++-
drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 249 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------
drivers/reset/reset-imx7.c | 1 +
[RFC 1/7] reset: imx7: Add the iMX8MP PCIe PHY PERST support
[RFC 2/7] dt-binding: phy: Add iMX8MP PCIe PHY binding
[RFC 3/7] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY support
[RFC 4/7] dt-bindings: imx6q-pcie: Add iMX8MP PCIe compatible string
[RFC 5/7] arm64: dts: imx8mp: add the iMX8MP PCIe support
[RFC 6/7] arm64: dts: imx8mp-evk: Add PCIe support
[RFC 7/7] PCI: imx6: Add the iMX8MP PCIe support
Add the i.MX8MP PCIe PHY PERST support.
Signed-off-by: Richard Zhu <[email protected]>
---
drivers/reset/reset-imx7.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 185a333df66c..d2408725eb2c 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -329,6 +329,7 @@ static int imx8mp_reset_set(struct reset_controller_dev *rcdev,
break;
case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
+ case IMX8MP_RESET_PCIEPHY_PERST:
value = assert ? 0 : bit;
break;
}
--
2.25.1
Add i.MX8MP PCIe PHY binding.
Signed-off-by: Richard Zhu <[email protected]>
---
Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
index b6421eedece3..3646b3ed4375 100644
--- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
@@ -16,6 +16,7 @@ properties:
compatible:
enum:
- fsl,imx8mm-pcie-phy
+ - fsl,imx8mp-pcie-phy
reg:
maxItems: 1
@@ -28,11 +29,12 @@ properties:
- const: ref
resets:
- maxItems: 1
+ maxItems: 2
reset-names:
items:
- const: pciephy
+ - const: perst
fsl,refclk-pad-mode:
description: |
--
2.25.1
Add PCIe support on i.MX8MP EVK board.
Signed-off-by: Richard Zhu <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 55 ++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 2eb943210678..ed77455a3f73 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -5,6 +5,7 @@
/dts-v1/;
+#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp.dtsi"
/ {
@@ -33,6 +34,12 @@ memory@40000000 {
<0x1 0x00000000 0 0xc0000000>;
};
+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
regulator-name = "can1-stby";
@@ -55,6 +62,17 @@ reg_can2_stby: regulator-can2-stby {
enable-active-high;
};
+ reg_pcie0: regulator-pcie {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0_reg>;
+ regulator-name = "MPCIE_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -297,6 +315,30 @@ pca6416: gpio@20 {
};
};
+&pcie_phy {
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ clocks = <&pcie0_refclk>;
+ clock-names = "ref";
+ status = "okay";
+};
+
+&pcie{
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_PCIE_ROOT>,
+ <&clk IMX8MP_CLK_HSIO_AXI>;
+ clock-names = "pcie", "pcie_aux", "pcie_bus";
+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+ <&clk IMX8MP_CLK_PCIE_AUX>;
+ assigned-clock-rates = <500000000>, <10000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
+ <&clk IMX8MP_SYS_PLL2_50M>;
+ vpcie-supply = <®_pcie0>;
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -442,6 +484,19 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
>;
};
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */
+ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41
+ >;
+ };
+
+ pinctrl_pcie0_reg: pcie0reggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41
+ >;
+ };
+
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
--
2.25.1
Add the i.MX8MP PCIe support.
Signed-off-by: Richard Zhu <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46 ++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index b40a5646f205..e7b3d8029e34 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/power/imx8mp-power.h>
+#include <dt-bindings/reset/imx8mp-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -375,7 +376,8 @@ iomuxc: pinctrl@30330000 {
};
gpr: iomuxc-gpr@30340000 {
- compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
+ compatible = "fsl,imx8mp-iomuxc-gpr",
+ "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
@@ -965,6 +967,17 @@ aips4: bus@32c00000 {
#size-cells = <1>;
ranges;
+ pcie_phy: pcie-phy@32f00000 {
+ compatible = "fsl,imx8mp-pcie-phy";
+ reg = <0x32f00000 0x10000>;
+ resets = <&src IMX8MP_RESET_PCIEPHY>,
+ <&src IMX8MP_RESET_PCIEPHY_PERST>;
+ reset-names = "pciephy", "perst";
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
hsio_blk_ctrl: blk-ctrl@32f10000 {
compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
reg = <0x32f10000 0x24>;
@@ -980,6 +993,37 @@ hsio_blk_ctrl: blk-ctrl@32f10000 {
};
};
+ pcie: pcie@33800000 {
+ compatible = "fsl,imx8mp-pcie";
+ reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ num-viewport = <4>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,max-link-speed = <3>;
+ linux,pci-domain = <0>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
+ resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "apps", "turnoff";
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+ status = "disabled";
+ };
+
gpu3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;
--
2.25.1