2022-04-11 11:56:43

by Rohit Agarwal

Subject: [PATCH 3/7] ARM: dts: qcom: sdx65: Add support for SDHCI controller

Add devicetree support for SDHCI controller found in Qualcomm SDX65
platform. The SDHCI controller is based on the MSM SDHCI v5 IP.

Signed-off-by: Rohit Agarwal <[email protected]>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 365df74..632ac78 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -168,6 +168,19 @@
#interrupt-cells = <2>;
};

+ sdhc_1: sdhci@8804000 {
+ compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x08804000 0x1000>;
+ reg-names = "hc_mem";
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
pdc: interrupt-controller@b210000 {
compatible = "qcom,sdx65-pdc", "qcom,pdc";
reg = <0xb210000 0x10000>;
--
2.7.4

2022-04-11 15:12:29

by Manivannan Sadhasivam

Subject: Re: [PATCH 3/7] ARM: dts: qcom: sdx65: Add support for SDHCI controller

On Mon, Apr 11, 2022 at 12:25:39PM +0530, Rohit Agarwal wrote:
> Add devicetree support for SDHCI controller found in Qualcomm SDX65
> platform. The SDHCI controller is based on the MSM SDHCI v5 IP.
>
> Signed-off-by: Rohit Agarwal <[email protected]>

Reviewed-by: Manivannan Sadhasivam <[email protected]>

Thanks,
Mani

> ---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 365df74..632ac78 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -168,6 +168,19 @@
> #interrupt-cells = <2>;
> };
>
> + sdhc_1: sdhci@8804000 {
> + compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x08804000 0x1000>;
> + reg-names = "hc_mem";
> + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> + clocks = <&gcc GCC_SDCC1_APPS_CLK>,
> + <&gcc GCC_SDCC1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> pdc: interrupt-controller@b210000 {
> compatible = "qcom,sdx65-pdc", "qcom,pdc";
> reg = <0xb210000 0x10000>;
> --
> 2.7.4
>