Hello,
This series adds devicetree nodes for SDX65. It adds
reserved memory nodes, SDHCI, smmu and tcsr mutex support.
Thanks,
Rohit.
Rohit Agarwal (7):
ARM: dts: qcom: sdx65: Add reserved memory nodes
dt-bindings: mmc: sdhci-msm: Document the SDX65 compatible
ARM: dts: qcom: sdx65: Add support for SDHCI controller
dt-bindings: arm-smmu: Add binding for SDX65 SMMU
ARM: dts: qcom: sdx65: Enable ARM SMMU
ARM: dts: qcom: sdx65: Add support for TCSR Mutex
ARM: dts: qcom: sdx65: Add Shared memory manager support
.../devicetree/bindings/iommu/arm,smmu.yaml | 1 +
.../devicetree/bindings/mmc/sdhci-msm.txt | 1 +
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 21 ++++
arch/arm/boot/dts/qcom-sdx65.dtsi | 110 +++++++++++++++++++++
4 files changed, 133 insertions(+)
--
2.7.4
Add smem node to support shared memory manager on SDX65 platform.
Signed-off-by: Rohit Agarwal <[email protected]>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 5c28c94..b0eec91 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -174,6 +174,12 @@
#hwlock-cells = <1>;
};
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
sdhc_1: sdhci@8804000 {
compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
--
2.7.4
The SDHCI controller on SDX65 is based on MSM SDHCI v5 IP. Hence,
document the compatible with "qcom,sdhci-msm-v5" as the fallback.
Signed-off-by: Rohit Agarwal <[email protected]>
---
Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
index 6a8cc26..e1023e8 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
@@ -24,6 +24,7 @@ Required properties:
"qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
"qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"
"qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
+ "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
"qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"
NOTE that some old device tree files may be floating around that only
have the string "qcom,sdhci-msm-v4" without the SoC compatible string
--
2.7.4
On Mon, Apr 11, 2022 at 12:25:36PM +0530, Rohit Agarwal wrote:
> Hello,
>
> This series adds devicetree nodes for SDX65. It adds
> reserved memory nodes, SDHCI, smmu and tcsr mutex support.
>
Please CC me to all SDX65 related patches as I'd like to review them.
Thanks,
Mani
> Thanks,
> Rohit.
>
> Rohit Agarwal (7):
> ARM: dts: qcom: sdx65: Add reserved memory nodes
> dt-bindings: mmc: sdhci-msm: Document the SDX65 compatible
> ARM: dts: qcom: sdx65: Add support for SDHCI controller
> dt-bindings: arm-smmu: Add binding for SDX65 SMMU
> ARM: dts: qcom: sdx65: Enable ARM SMMU
> ARM: dts: qcom: sdx65: Add support for TCSR Mutex
> ARM: dts: qcom: sdx65: Add Shared memory manager support
>
> .../devicetree/bindings/iommu/arm,smmu.yaml | 1 +
> .../devicetree/bindings/mmc/sdhci-msm.txt | 1 +
> arch/arm/boot/dts/qcom-sdx65-mtp.dts | 21 ++++
> arch/arm/boot/dts/qcom-sdx65.dtsi | 110 +++++++++++++++++++++
> 4 files changed, 133 insertions(+)
>
> --
> 2.7.4
>
Add devicetree binding for Qualcomm SDX65 SMMU.
Signed-off-by: Rohit Agarwal <[email protected]>
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index da5381c..1f99bff 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -39,6 +39,7 @@ properties:
- qcom,sc8180x-smmu-500
- qcom,sdm845-smmu-500
- qcom,sdx55-smmu-500
+ - qcom,sdx65-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm8150-smmu-500
- qcom,sm8250-smmu-500
--
2.7.4
Add a node for the ARM SMMU found in the SDX65.
Signed-off-by: Rohit Agarwal <[email protected]>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 40 +++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 632ac78..2481769 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -181,6 +181,46 @@
status = "disabled";
};
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,sdx65-smmu-500", "arm,mmu-500";
+ reg = <0x15000000 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
pdc: interrupt-controller@b210000 {
compatible = "qcom,sdx65-pdc", "qcom,pdc";
reg = <0xb210000 0x10000>;
--
2.7.4