This patch set is to add bolero digital macros, WCD and maxim codecs nodes
for audio on sc7280 based platforms.
This patch set depends on:
-- https://patchwork.kernel.org/project/linux-arm-msm/list/?series=631506
-- https://patchwork.kernel.org/project/linux-arm-msm/list/?series=601249
-- https://patchwork.kernel.org/project/linux-arm-msm/list/?series=634203
-- Clock reset control patches
Changes Since V8:
-- Split patches as per sc7280 CRD revision 3, 4 and 5 boards.
-- Add corresponding dt nodes for herobrine crd boards.
-- Update dai-link node names as per dt-bindings in sound node.
-- Add reg property in sound node as per dt-bindings which was removed in previous series.
-- Fix typo errors.
-- Update wcd codec pin control properties in board specific files.
Changes Since V7:
-- Remove redundant interrupt names in soundwire node.
-- Fix typo errors.
-- Remove redundant reg property in sound node.
-- Rebased on top of latest kernel tip.
Changes Since V6:
-- Modify link-names and audio routing in a sound node.
-- Move amp_en pin control node to appropriate consumer patch.
-- Split patches as per digital macro codecs and board specific codecs and sort it.
-- Modify label and node names to lpass specific.
Changes Since V5:
-- Move soc specific bolero digital codec nodes to soc specific file.
-- Bring wcd938x codec reset pin control and US/EURO HS selection nodes from other series.
-- Change node name and remove redundant status property in sound node.
Changes Since V4:
-- Update nodes in sorting order.
-- Update DTS node names as per dt-bindings.
-- Update Node properties in proper order.
-- Update missing pinctrl properties like US/EURO HS selection, wcd reset control.
-- Remove redundant labels.
-- Remove unused size cells and address cells in tx macro node.
-- Keep all same nodes at one place, which are defined in same file.
-- Add max98360a codec node to herobrine board specific targets.
Changes Since V3:
-- Move digital codec macro nodes to board specific dtsi file.
-- Update pin controls in lpass cpu node.
-- Update dependency patch list.
-- Create patches on latest kernel.
Changes Since V2:
-- Add power domains to digital codec macro nodes.
-- Change clock node usage in lpass cpu node.
-- Add codec mem clock to lpass cpu node.
-- Modify the node names to be generic.
-- Move sound and codec nodes to root node.
-- sort dai links as per reg.
-- Fix typo errors.
Changes Since V1:
-- Update the commit message of cpu node patch.
-- Add gpio control property to support Euro headset in wcd938x node.
-- Fix clock properties in lpass cpu and digital codec macro node.
Srinivasa Rao Mandadapu (12):
arm64: dts: qcom: sc7280: Add nodes for soundwire and va tx rx digital
macro codecs
arm64: dts: qcom: sc7280: Enable digital codecs and soundwire for CRD
1.0 and CRD 2.0
arm64: dts: qcom: sc7280: Enable digital codecs and soundwire for CRD
3.0/3.1
arm64: dts: qcom: sc7280: Add wcd9385 codec node for CRD 1.0 and CRD
2.0
arm64: dts: qcom: sc7280: Add wcd9385 codec node for CRD 3.0/3.1
arm64: dts: qcom: sc7280: Add max98360a codec for CRD 1.0 and 2.0
arm64: dts: qcom: sc7280: Add max98360a codec node for CRD 3.0/3.1
arm64: dts: qcom: sc7280: Add lpass cpu node
arm64: dts: qcom: sc7280: Enable lpass cpu node for CRD 1.0 and CRD
2.0
arm64: dts: qcom: sc7280: Enable lpass cpu node for CRD 3.0/3.1
arm64: dts: qcom: sc7280: Add sound node for CRD 1.0 and CRD 2.0
arm64: dts: qcom: sc7280: Add sound node for CRD 3.0/3.1
arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 31 +++
arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 213 ++++++++++++++++++++
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 8 +
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 225 ++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 190 ++++++++++++++++++
5 files changed, 667 insertions(+)
--
2.7.4
Add max98360a codec node for audio use case on revision 3 and
4 (aka CRD 1.0 and 2.0) boards.
Add amp_en node for max98360a codec pin control.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index b711ad0..24196a1 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -20,6 +20,14 @@
serial1 = &uart7;
};
+ max98360a: audio-codec-0 {
+ compatible = "maxim,max98360a";
+ pinctrl-names = "default";
+ pinctrl-0 = <&_en>;
+ sdmode-gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
+ #sound-dai-cells = <0>;
+ };
+
wcd938x: audio-codec-1 {
compatible = "qcom,wcd9385-codec";
pinctrl-names = "default", "sleep";
@@ -624,6 +632,12 @@
};
&tlmm {
+ amp_en: amp-en {
+ pins = "gpio63";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
bt_en: bt-en {
pins = "gpio85";
function = "gpio";
--
2.7.4
Add dt nodes for sound card support on rev5 (aka CRD 3.0/3.1) boards,
which is using WCD938x headset playback, capture, I2S speaker playback
and DMICs via VA macro.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 98 +++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
index 4033d2a..bc6dbcc 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
@@ -42,6 +42,104 @@
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
#sound-dai-cells = <1>;
};
+
+ sound: sound {
+ compatible = "google,sc7280-herobrine";
+ model = "sc7280-wcd938x-max98360a-1mic";
+
+ audio-routing =
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC1", "MIC BIAS1",
+ "AMIC2", "MIC BIAS2",
+ "VA DMIC0", "MIC BIAS1",
+ "VA DMIC1", "MIC BIAS1",
+ "VA DMIC2", "MIC BIAS3",
+ "VA DMIC3", "MIC BIAS3",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT";
+
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <0>;
+
+ dai-link@0 {
+ link-name = "MAX98360A";
+ reg = <MI2S_SECONDARY>;
+
+ cpu {
+ sound-dai = <&lpass_cpu MI2S_SECONDARY>;
+ };
+
+ codec {
+ sound-dai = <&max98360a>;
+ };
+ };
+
+ dai-link@1 {
+ link-name = "DisplayPort";
+ reg = <LPASS_DP_RX>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_DP_RX>;
+ };
+
+ codec {
+ sound-dai = <&mdss_dp>;
+ };
+ };
+
+ dai-link@2 {
+ link-name = "WCD9385 Playback";
+ reg = <LPASS_CDC_DMA_RX0>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 0>, <&swr0 0>, <&lpass_rx_macro 0>;
+ };
+ };
+
+ dai-link@3 {
+ link-name = "WCD9385 Capture";
+ reg = <LPASS_CDC_DMA_TX3>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 1>, <&swr1 0>, <&lpass_tx_macro 0>;
+ };
+ };
+
+ dai-link@4 {
+ link-name = "DMIC";
+ reg = <LPASS_CDC_DMA_VA_TX0>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>;
+ };
+
+ codec {
+ sound-dai = <&lpass_va_macro 0>;
+ };
+ };
+ };
};
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
--
2.7.4
Add lpass cpu node for audio on sc7280 based platforms.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
Reviewed-by: Matthias Kaehlcke <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 62 ++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 23e09fa..e355c33 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -21,6 +21,7 @@
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/sound/qcom,lpass.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -2195,6 +2196,67 @@
#power-domain-cells = <1>;
};
+ lpass_cpu: audio@3987000 {
+ compatible = "qcom,sc7280-lpass-cpu";
+
+ reg = <0 0x03987000 0 0x68000>,
+ <0 0x03b00000 0 0x29000>,
+ <0 0x03260000 0 0xc000>,
+ <0 0x03280000 0 0x29000>,
+ <0 0x03340000 0 0x29000>,
+ <0 0x0336c000 0 0x3000>;
+ reg-names = "lpass-hdmiif",
+ "lpass-lpaif",
+ "lpass-rxtx-cdc-dma-lpm",
+ "lpass-rxtx-lpaif",
+ "lpass-va-lpaif",
+ "lpass-va-cdc-dma-lpm";
+
+ iommus = <&apps_smmu 0x1820 0>,
+ <&apps_smmu 0x1821 0>,
+ <&apps_smmu 0x1832 0>;
+
+ power-domains = <&rpmhpd SC7280_LCX>;
+ power-domain-names = "lcx";
+ required-opps = <&rpmhpd_opp_nom>;
+
+ clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>,
+ <&lpass_audiocc LPASS_AUDIO_CC_EXT_MCLK0_CLK>,
+ <&lpasscore LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>,
+ <&lpasscore LPASS_CORE_CC_EXT_IF0_IBIT_CLK>,
+ <&lpasscore LPASS_CORE_CC_EXT_IF1_IBIT_CLK>,
+ <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>,
+ <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>,
+ <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>,
+ <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>,
+ <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>;
+ clock-names = "aon_cc_audio_hm_h",
+ "audio_cc_ext_mclk0",
+ "core_cc_sysnoc_mport_core",
+ "core_cc_ext_if0_ibit",
+ "core_cc_ext_if1_ibit",
+ "audio_cc_codec_mem",
+ "audio_cc_codec_mem0",
+ "audio_cc_codec_mem1",
+ "audio_cc_codec_mem2",
+ "aon_cc_va_mem0";
+
+ #sound-dai-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpass-irq-lpaif",
+ "lpass-irq-hdmi",
+ "lpass-irq-vaif",
+ "lpass-irq-rxtxif";
+
+ status = "disabled";
+ };
+
lpass_hm: clock-controller@3c00000 {
compatible = "qcom,sc7280-lpasshm";
reg = <0 0x3c00000 0 0x28>;
--
2.7.4
Add wcd9385 codec node for audio use case on CRD rev5 (aka CRD 3.0/3.1)
boards. Add tlmm gpio property for switching CTIA/OMTP Headset.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 52 +++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
index d0794f2..d6a3086 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
@@ -12,6 +12,36 @@
/ {
model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)";
compatible = "google,hoglin", "qcom,sc7280";
+
+ wcd938x: audio-codec-1 {
+ compatible = "qcom,wcd9385-codec";
+ pinctrl-names = "default", "sleep", "us_euro_hs_sel";
+ pinctrl-0 = <&wcd_reset_n>;
+ pinctrl-1 = <&wcd_reset_n_sleep>;
+ pinctrl-2 = <&us_euro_hs_sel>;
+
+ reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
+ us-euro-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ vdd-rxtx-supply = <&vreg_l18b_1p8>;
+ vdd-io-supply = <&vreg_l18b_1p8>;
+ vdd-buck-supply = <&vreg_l17b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob>;
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000
+ 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ #sound-dai-cells = <1>;
+ };
};
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
@@ -345,4 +375,26 @@ ap_ts_pen_1v8: &i2c13 {
"",
"",
"";
+
+ us_euro_hs_sel: us-euro-hs-sel {
+ pins = "gpio81";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ wcd_reset_n: wcd-reset-n {
+ pins = "gpio83";
+ function = "gpio";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ wcd_reset_n_sleep: wcd-reset-n-sleep {
+ pins = "gpio83";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ output-low;
+ };
};
--
2.7.4
Enable lpass cpu node for audio on sc7280 based platforms of revision 3
and 4 (aka CRD 1.0 and 2.0) boards.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
Reviewed-by: Matthias Kaehlcke <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 24196a1..2e991e8 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -274,6 +274,34 @@
modem-init;
};
+&lpass_cpu {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;
+
+ dai-link@1 {
+ reg = <MI2S_SECONDARY>;
+ qcom,playback-sd-lines = <0>;
+ };
+
+ dai-link@5 {
+ reg = <LPASS_DP_RX>;
+ };
+
+ dai-link@6 {
+ reg = <LPASS_CDC_DMA_RX0>;
+ };
+
+ dai-link@19 {
+ reg = <LPASS_CDC_DMA_TX3>;
+ };
+
+ dai-link@25 {
+ reg = <LPASS_CDC_DMA_VA_TX0>;
+ };
+};
+
&lpass_rx_macro {
status = "okay";
};
--
2.7.4
On Thu, Apr 21, 2022 at 08:17:33PM +0530, Srinivasa Rao Mandadapu wrote:
> Subject: arm64: dts: qcom: sc7280: Add max98360a codec for CRD 1.0 and 2.0
nit: and the IDP boards?
> Add max98360a codec node for audio use case on revision 3 and
> 4 (aka CRD 1.0 and 2.0) boards.
> Add amp_en node for max98360a codec pin control.
>
> Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
> Co-developed-by: Venkata Prasad Potturu <[email protected]>
> Signed-off-by: Venkata Prasad Potturu <[email protected]>
Reviewed-by: Matthias Kaehlcke <[email protected]>
On Thu, Apr 21, 2022 at 08:17:39PM +0530, Srinivasa Rao Mandadapu wrote:
> Add dt nodes for sound card support on rev5 (aka CRD 3.0/3.1) boards,
> which is using WCD938x headset playback, capture, I2S speaker playback
> and DMICs via VA macro.
>
> Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
> Co-developed-by: Venkata Prasad Potturu <[email protected]>
> Signed-off-by: Venkata Prasad Potturu <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 98 +++++++++++++++++++++++
> 1 file changed, 98 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
> index 4033d2a..bc6dbcc 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
> @@ -42,6 +42,104 @@
> qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
> #sound-dai-cells = <1>;
> };
> +
> + sound: sound {
> + compatible = "google,sc7280-herobrine";
> + model = "sc7280-wcd938x-max98360a-1mic";
> +
> + audio-routing =
> + "IN1_HPHL", "HPHL_OUT",
> + "IN2_HPHR", "HPHR_OUT",
> + "AMIC1", "MIC BIAS1",
> + "AMIC2", "MIC BIAS2",
> + "VA DMIC0", "MIC BIAS1",
> + "VA DMIC1", "MIC BIAS1",
> + "VA DMIC2", "MIC BIAS3",
> + "VA DMIC3", "MIC BIAS3",
> + "TX SWR_ADC0", "ADC1_OUTPUT",
> + "TX SWR_ADC1", "ADC2_OUTPUT",
> + "TX SWR_ADC2", "ADC3_OUTPUT",
> + "TX SWR_DMIC0", "DMIC1_OUTPUT",
> + "TX SWR_DMIC1", "DMIC2_OUTPUT",
> + "TX SWR_DMIC2", "DMIC3_OUTPUT",
> + "TX SWR_DMIC3", "DMIC4_OUTPUT",
> + "TX SWR_DMIC4", "DMIC5_OUTPUT",
> + "TX SWR_DMIC5", "DMIC6_OUTPUT",
> + "TX SWR_DMIC6", "DMIC7_OUTPUT",
> + "TX SWR_DMIC7", "DMIC8_OUTPUT";
> +
> + qcom,msm-mbhc-hphl-swh = <1>;
> + qcom,msm-mbhc-gnd-swh = <1>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #sound-dai-cells = <0>;
> +
> + dai-link@0 {
> + link-name = "MAX98360A";
> + reg = <MI2S_SECONDARY>;
same comment as for "arm64: dts: qcom: sc7280: Add sound node for CRD
1.0 and CRD 2.0", i.e. use the link number for 'reg' instead of the lpass
DAI id.
> +
> + cpu {
> + sound-dai = <&lpass_cpu MI2S_SECONDARY>;
> + };
> +
> + codec {
> + sound-dai = <&max98360a>;
> + };
> + };
> +
> + dai-link@1 {
> + link-name = "DisplayPort";
> + reg = <LPASS_DP_RX>;
> +
> + cpu {
> + sound-dai = <&lpass_cpu LPASS_DP_RX>;
> + };
> +
> + codec {
> + sound-dai = <&mdss_dp>;
> + };
> + };
> +
> + dai-link@2 {
> + link-name = "WCD9385 Playback";
> + reg = <LPASS_CDC_DMA_RX0>;
> +
> + cpu {
> + sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>;
> + };
> +
> + codec {
> + sound-dai = <&wcd938x 0>, <&swr0 0>, <&lpass_rx_macro 0>;
> + };
> + };
> +
> + dai-link@3 {
> + link-name = "WCD9385 Capture";
> + reg = <LPASS_CDC_DMA_TX3>;
> +
> + cpu {
> + sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>;
> + };
> +
> + codec {
> + sound-dai = <&wcd938x 1>, <&swr1 0>, <&lpass_tx_macro 0>;
> + };
> + };
> +
> + dai-link@4 {
> + link-name = "DMIC";
> + reg = <LPASS_CDC_DMA_VA_TX0>;
> +
> + cpu {
> + sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>;
> + };
> +
> + codec {
> + sound-dai = <&lpass_va_macro 0>;
> + };
> + };
> + };
> };
Enable rx, tx and va macro codecs and soundwire nodes on revision 3
and 4 (aka CRD 1.0 and 2.0) boards.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 35 ++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 2f863c0..6cb5fc4 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -238,6 +238,19 @@
modem-init;
};
+&lpass_rx_macro {
+ status = "okay";
+};
+
+&lpass_tx_macro {
+ status = "okay";
+};
+
+&lpass_va_macro {
+ status = "okay";
+ vdd-micb-supply = <&vreg_bob>;
+};
+
&pcie1 {
status = "okay";
perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;
@@ -298,6 +311,28 @@
cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
};
+&swr0 {
+ status = "okay";
+
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010d00";
+ reg = <0 4>;
+ #sound-dai-cells = <1>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010d00";
+ reg = <0 3>;
+ #sound-dai-cells = <1>;
+ qcom,tx-port-mapping = <1 2 3 4>;
+ };
+};
+
&uart5 {
compatible = "qcom,geni-debug-uart";
status = "okay";
--
2.7.4
Enable lpass cpu node for audio on sc7280 based platforms of rev5
(aka CRD 3.0/3.1) boards.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 28 +++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
index d6a3086..4033d2a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
@@ -99,6 +99,34 @@ ap_ts_pen_1v8: &i2c13 {
};
};
+&lpass_cpu {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;
+
+ dai-link@1 {
+ reg = <MI2S_SECONDARY>;
+ qcom,playback-sd-lines = <0>;
+ };
+
+ dai-link@5 {
+ reg = <LPASS_DP_RX>;
+ };
+
+ dai-link@6 {
+ reg = <LPASS_CDC_DMA_RX0>;
+ };
+
+ dai-link@19 {
+ reg = <LPASS_CDC_DMA_TX3>;
+ };
+
+ dai-link@25 {
+ reg = <LPASS_CDC_DMA_VA_TX0>;
+ };
+};
+
&lpass_rx_macro {
status = "okay";
};
--
2.7.4
On Thu, Apr 21, 2022 at 08:17:32PM +0530, Srinivasa Rao Mandadapu wrote:
> Add wcd9385 codec node for audio use case on CRD rev5 (aka CRD 3.0/3.1)
nit: rev5+
> boards. Add tlmm gpio property for switching CTIA/OMTP Headset.
>
> Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
> Co-developed-by: Venkata Prasad Potturu <[email protected]>
> Signed-off-by: Venkata Prasad Potturu <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 52 +++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
> index d0794f2..d6a3086 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
> @@ -12,6 +12,36 @@
> / {
> model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)";
> compatible = "google,hoglin", "qcom,sc7280";
> +
> + wcd938x: audio-codec-1 {
wcd9385 (same for the CRD <= 2.0, I missed it there).
> + compatible = "qcom,wcd9385-codec";
> + pinctrl-names = "default", "sleep", "us_euro_hs_sel";
> + pinctrl-0 = <&wcd_reset_n>;
> + pinctrl-1 = <&wcd_reset_n_sleep>;
> + pinctrl-2 = <&us_euro_hs_sel>;
This looks wrong, see my comment on the CRD <= 2.0 patch
(https://patchwork.kernel.org/project/linux-arm-msm/patch/[email protected]/)
> +
> + reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
> + us-euro-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
> +
> + qcom,rx-device = <&wcd_rx>;
> + qcom,tx-device = <&wcd_tx>;
> +
> + vdd-rxtx-supply = <&vreg_l18b_1p8>;
> + vdd-io-supply = <&vreg_l18b_1p8>;
> + vdd-buck-supply = <&vreg_l17b_1p8>;
> + vdd-mic-bias-supply = <&vreg_bob>;
> +
> + qcom,micbias1-microvolt = <1800000>;
> + qcom,micbias2-microvolt = <1800000>;
> + qcom,micbias3-microvolt = <1800000>;
> + qcom,micbias4-microvolt = <1800000>;
> +
> + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000
> + 500000 500000 500000>;
> + qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
> + qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
> + #sound-dai-cells = <1>;
> + };
The wcd9385 is on the qcard, so I think this node should be added to
sc7280-qcard.dtsi and be marked as "disabled". This file can then just
set the status to "okay". Future boards that use the wcd could do the
same, rather than adding a copy of this node to their .dts file.
> };
>
> /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
> @@ -345,4 +375,26 @@ ap_ts_pen_1v8: &i2c13 {
> "",
> "",
> "";
> +
> + us_euro_hs_sel: us-euro-hs-sel {
> + pins = "gpio81";
> + function = "gpio";
> + bias-pull-down;
> + drive-strength = <2>;
> + };
> +
> + wcd_reset_n: wcd-reset-n {
> + pins = "gpio83";
> + function = "gpio";
> + drive-strength = <8>;
> + output-high;
> + };
> +
> + wcd_reset_n_sleep: wcd-reset-n-sleep {
> + pins = "gpio83";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-disable;
> + output-low;
> + };
These are also on the qcard, please move the nodes to sc7280-qcard.dtsi
On Thu, Apr 21, 2022 at 08:17:37PM +0530, Srinivasa Rao Mandadapu wrote:
> Enable lpass cpu node for audio on sc7280 based platforms of rev5
> (aka CRD 3.0/3.1) boards.
nit: the patch does a bit more than purely 'enabling' the node.
> Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
> Co-developed-by: Venkata Prasad Potturu <[email protected]>
> Signed-off-by: Venkata Prasad Potturu <[email protected]>
Reviewed-by: Matthias Kaehlcke <[email protected]>
SC7280 has VA, TX and RX macros with SoundWire Controllers to attach with
external codecs using soundwire masters. Add these nodes for sc7280 based
platforms audio use case.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
Reviewed-by: Matthias Kaehlcke <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 128 +++++++++++++++++++++++++++++++++++
1 file changed, 128 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index f428344..23e09fa 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2035,6 +2035,114 @@
#clock-cells = <1>;
};
+ lpass_rx_macro: codec@3200000 {
+ compatible = "qcom,sc7280-lpass-rx-macro";
+ reg = <0 0x03200000 0 0x1000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&lpass_rx_swr>;
+
+ clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
+ <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
+ <&lpass_va_macro>;
+ clock-names = "mclk", "npl", "fsgen";
+
+ power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
+ <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
+ power-domain-names = "macro", "dcodec";
+
+ #clock-cells = <0>;
+ #sound-dai-cells = <1>;
+
+ status = "disabled";
+ };
+
+ swr0: soundwire@3210000 {
+ compatible = "qcom,soundwire-v1.6.0";
+ reg = <0 0x03210000 0 0x2000>;
+
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lpass_rx_macro>;
+ clock-names = "iface";
+
+ qcom,din-ports = <0>;
+ qcom,dout-ports = <5>;
+
+ resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
+ reset-names = "swr_audio_cgcr";
+
+ qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
+ qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
+ qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
+
+ #sound-dai-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ lpass_tx_macro: codec@3220000 {
+ compatible = "qcom,sc7280-lpass-tx-macro";
+ reg = <0 0x03220000 0 0x1000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&lpass_tx_swr>;
+
+ clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
+ <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
+ <&lpass_va_macro>;
+ clock-names = "mclk", "npl", "fsgen";
+
+ power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
+ <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
+ power-domain-names = "macro", "dcodec";
+
+ #clock-cells = <0>;
+ #sound-dai-cells = <1>;
+
+ status = "disabled";
+ };
+
+ swr1: soundwire@3230000 {
+ compatible = "qcom,soundwire-v1.6.0";
+ reg = <0 0x03230000 0 0x2000>;
+
+ interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lpass_tx_macro>;
+ clock-names = "iface";
+
+ qcom,din-ports = <3>;
+ qcom,dout-ports = <0>;
+
+ resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>;
+ reset-names = "swr_audio_cgcr";
+
+ qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
+ qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
+ qcom,port-offset = <1>;
+
+ #sound-dai-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
lpass_audiocc: clock-controller@3300000 {
compatible = "qcom,sc7280-lpassaudiocc";
reg = <0 0x03300000 0 0x30000>;
@@ -2046,6 +2154,26 @@
#power-domain-cells = <1>;
};
+ lpass_va_macro: codec@3370000 {
+ compatible = "qcom,sc7280-lpass-va-macro";
+ reg = <0 0x03370000 0 0x1000>;
+
+ pinctrl-0 = <&lpass_dmic01>;
+ pinctrl-names = "default";
+
+ clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>;
+ clock-names = "mclk";
+
+ power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
+ <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
+ power-domain-names = "macro", "dcodec";
+
+ #clock-cells = <0>;
+ #sound-dai-cells = <1>;
+
+ status = "disabled";
+ };
+
lpass_aon: clock-controller@3380000 {
compatible = "qcom,sc7280-lpassaoncc";
reg = <0 0x03380000 0 0x30000>;
--
2.7.4
Enable rx, tx and va macro codecs and soundwire nodes for
CRD rev5 (aka CRD 3.0/3.1) boards.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 35 +++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
index fd6eadc..d0794f2 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
@@ -69,6 +69,19 @@ ap_ts_pen_1v8: &i2c13 {
};
};
+&lpass_rx_macro {
+ status = "okay";
+};
+
+&lpass_tx_macro {
+ status = "okay";
+};
+
+&lpass_va_macro {
+ status = "okay";
+ vdd-micb-supply = <&vreg_bob>;
+};
+
/* For nvme */
&pcie1 {
status = "okay";
@@ -89,6 +102,28 @@ ap_ts_pen_1v8: &i2c13 {
status = "okay";
};
+&swr0 {
+ status = "okay";
+
+ wcd_rx: codec@0,4 {
+ compatible = "sdw20217010d00";
+ reg = <0 4>;
+ #sound-dai-cells = <1>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ wcd_tx: codec@0,3 {
+ compatible = "sdw20217010d00";
+ reg = <0 3>;
+ #sound-dai-cells = <1>;
+ qcom,tx-port-mapping = <1 2 3 4>;
+ };
+};
+
/* PINCTRL - BOARD-SPECIFIC */
/*
--
2.7.4
Add max98360a codec node for audio use case on CRD rev5
(aka CRD 3.0/3.1) boards.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
index d58045d..f247403 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
@@ -20,6 +20,14 @@
#include "sc7280-chrome-common.dtsi"
/ {
+ max98360a: audio-codec-0 {
+ compatible = "maxim,max98360a";
+ pinctrl-names = "default";
+ pinctrl-0 = <&_en>;
+ sdmode-gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
+ #sound-dai-cells = <0>;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
--
2.7.4
Add dt nodes for sound card support on revision 3 and 4
(aka CRD 1.0 and 2.0) boards, which is using WCD938x headset
playback, capture, I2S speaker playback and DMICs via VA macro.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 23 +++++++
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 98 ++++++++++++++++++++++++++++++
2 files changed, 121 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
index 462d655..763d2bf 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
@@ -87,6 +87,29 @@ ap_ts_pen_1v8: &i2c13 {
pins = "gpio51";
};
+&sound {
+ audio-routing =
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC1", "MIC BIAS1",
+ "AMIC2", "MIC BIAS2",
+ "VA DMIC0", "MIC BIAS1",
+ "VA DMIC1", "MIC BIAS1",
+ "VA DMIC2", "MIC BIAS3",
+ "VA DMIC3", "MIC BIAS3",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT";
+};
+
&wcd938x {
pinctrl-names = "default", "sleep", "us_euro_hs_sel";
pinctrl-0 = <&wcd_reset_n>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 2e991e8..f2ad0c6 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -85,6 +85,104 @@
pinctrl-names = "default";
pinctrl-0 = <&nvme_pwren>;
};
+
+ sound: sound {
+ compatible = "google,sc7280-herobrine";
+ model = "sc7280-wcd938x-max98360a-1mic";
+
+ audio-routing =
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC1", "MIC BIAS1",
+ "AMIC2", "MIC BIAS2",
+ "VA DMIC0", "MIC BIAS3",
+ "VA DMIC1", "MIC BIAS3",
+ "VA DMIC2", "MIC BIAS1",
+ "VA DMIC3", "MIC BIAS1",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT";
+
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <0>;
+
+ dai-link@0 {
+ link-name = "MAX98360A";
+ reg = <MI2S_SECONDARY>;
+
+ cpu {
+ sound-dai = <&lpass_cpu MI2S_SECONDARY>;
+ };
+
+ codec {
+ sound-dai = <&max98360a>;
+ };
+ };
+
+ dai-link@1 {
+ link-name = "DisplayPort";
+ reg = <LPASS_DP_RX>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_DP_RX>;
+ };
+
+ codec {
+ sound-dai = <&mdss_dp>;
+ };
+ };
+
+ dai-link@2 {
+ link-name = "WCD9385 Playback";
+ reg = <LPASS_CDC_DMA_RX0>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 0>, <&swr0 0>, <&lpass_rx_macro 0>;
+ };
+ };
+
+ dai-link@3 {
+ link-name = "WCD9385 Capture";
+ reg = <LPASS_CDC_DMA_TX3>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>;
+ };
+
+ codec {
+ sound-dai = <&wcd938x 1>, <&swr1 0>, <&lpass_tx_macro 0>;
+ };
+ };
+
+ dai-link@4 {
+ link-name = "DMIC";
+ reg = <LPASS_CDC_DMA_VA_TX0>;
+
+ cpu {
+ sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>;
+ };
+
+ codec {
+ sound-dai = <&lpass_va_macro 0>;
+ };
+ };
+ };
};
&apps_rsc {
--
2.7.4
Add wcd9385 codec node for audio use case on sc7280 based platforms
of revision 3 and 4 (aka CRD 1.0 and 2.0).
Add tlmm gpio property for switching CTIA/OMTP Headset.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 8 +++++
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 50 ++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
index 344338a..462d655 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
@@ -87,6 +87,14 @@ ap_ts_pen_1v8: &i2c13 {
pins = "gpio51";
};
+&wcd938x {
+ pinctrl-names = "default", "sleep", "us_euro_hs_sel";
+ pinctrl-0 = <&wcd_reset_n>;
+ pinctrl-1 = <&wcd_reset_n_sleep>;
+ pinctrl-2 = <&us_euro_hs_sel>;
+ us-euro-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+};
+
&tlmm {
tp_int_odl: tp-int-odl {
pins = "gpio7";
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 6cb5fc4..b711ad0 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -20,6 +20,34 @@
serial1 = &uart7;
};
+ wcd938x: audio-codec-1 {
+ compatible = "qcom,wcd9385-codec";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&wcd_reset_n>;
+ pinctrl-1 = <&wcd_reset_n_sleep>;
+
+ reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
+
+ qcom,rx-device = <&wcd_rx>;
+ qcom,tx-device = <&wcd_tx>;
+
+ vdd-rxtx-supply = <&vreg_l18b_1p8>;
+ vdd-io-supply = <&vreg_l18b_1p8>;
+ vdd-buck-supply = <&vreg_l17b_1p8>;
+ vdd-mic-bias-supply = <&vreg_bob>;
+
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000
+ 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ #sound-dai-cells = <1>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
label = "gpio-keys";
@@ -678,6 +706,28 @@
function = "gpio";
bias-pull-down;
};
+
+ us_euro_hs_sel: us-euro-hs-sel {
+ pins = "gpio81";
+ function = "gpio";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ wcd_reset_n: wcd-reset-n {
+ pins = "gpio83";
+ function = "gpio";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ wcd_reset_n_sleep: wcd-reset-n-sleep {
+ pins = "gpio83";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ output-low;
+ };
};
&remoteproc_wpss {
--
2.7.4
On 4/21/2022 10:27 PM, Matthias Kaehlcke wrote:
Thanks for your time Matthias!!!
> On Thu, Apr 21, 2022 at 08:17:32PM +0530, Srinivasa Rao Mandadapu wrote:
>> Add wcd9385 codec node for audio use case on CRD rev5 (aka CRD 3.0/3.1)
> nit: rev5+
Okay.
>> boards. Add tlmm gpio property for switching CTIA/OMTP Headset.
>>
>> Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
>> Co-developed-by: Venkata Prasad Potturu <[email protected]>
>> Signed-off-by: Venkata Prasad Potturu <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 52 +++++++++++++++++++++++
>> 1 file changed, 52 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
>> index d0794f2..d6a3086 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
>> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
>> @@ -12,6 +12,36 @@
>> / {
>> model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)";
>> compatible = "google,hoglin", "qcom,sc7280";
>> +
>> + wcd938x: audio-codec-1 {
> wcd9385 (same for the CRD <= 2.0, I missed it there).
Okay.
>
>> + compatible = "qcom,wcd9385-codec";
>
>
>> + pinctrl-names = "default", "sleep", "us_euro_hs_sel";
>> + pinctrl-0 = <&wcd_reset_n>;
>> + pinctrl-1 = <&wcd_reset_n_sleep>;
>> + pinctrl-2 = <&us_euro_hs_sel>;
> This looks wrong, see my comment on the CRD <= 2.0 patch
> (https://patchwork.kernel.org/project/linux-arm-msm/patch/[email protected]/)
Okay. Will modify accordingly.
>
>> +
>> + reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
>> + us-euro-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
>> +
>> + qcom,rx-device = <&wcd_rx>;
>> + qcom,tx-device = <&wcd_tx>;
>> +
>> + vdd-rxtx-supply = <&vreg_l18b_1p8>;
>> + vdd-io-supply = <&vreg_l18b_1p8>;
>> + vdd-buck-supply = <&vreg_l17b_1p8>;
>> + vdd-mic-bias-supply = <&vreg_bob>;
>> +
>> + qcom,micbias1-microvolt = <1800000>;
>> + qcom,micbias2-microvolt = <1800000>;
>> + qcom,micbias3-microvolt = <1800000>;
>> + qcom,micbias4-microvolt = <1800000>;
>> +
>> + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000
>> + 500000 500000 500000>;
>> + qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
>> + qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
>> + #sound-dai-cells = <1>;
>> + };
> The wcd9385 is on the qcard, so I think this node should be added to
> sc7280-qcard.dtsi and be marked as "disabled". This file can then just
> set the status to "okay". Future boards that use the wcd could do the
> same, rather than adding a copy of this node to their .dts file.
Okay. Will move to qcard dtsi file.
>
>> };
>>
>> /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
>> @@ -345,4 +375,26 @@ ap_ts_pen_1v8: &i2c13 {
>> "",
>> "",
>> "";
>> +
>> + us_euro_hs_sel: us-euro-hs-sel {
>> + pins = "gpio81";
>> + function = "gpio";
>> + bias-pull-down;
>> + drive-strength = <2>;
>> + };
>> +
>> + wcd_reset_n: wcd-reset-n {
>> + pins = "gpio83";
>> + function = "gpio";
>> + drive-strength = <8>;
>> + output-high;
>> + };
>> +
>> + wcd_reset_n_sleep: wcd-reset-n-sleep {
>> + pins = "gpio83";
>> + function = "gpio";
>> + drive-strength = <8>;
>> + bias-disable;
>> + output-low;
>> + };
> These are also on the qcard, please move the nodes to sc7280-qcard.dtsi
Okay.