Enable QPIC NAND devicetree node for Qualcomm SDX65-MTP board.
Signed-off-by: Kaushal Kumar <[email protected]>
---
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index 5c5fcb0..3628104 100644
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -72,6 +72,21 @@
status = "ok";
};
+&qpic_nand {
+ status = "ok";
+
+ nand@0 {
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ /* ico and efs2 partitions are secured */
+ secure-regions = /bits/ 64 <0x500000 0x500000
+ 0xa00000 0xb00000>;
+ };
+};
+
&apps_rsc {
pmx65-rpmh-regulators {
compatible = "qcom,pmx65-rpmh-regulators";
--
2.7.4
On Sat, Apr 30, 2022 at 08:30:10AM -0700, Kaushal Kumar wrote:
> Enable QPIC NAND devicetree node for Qualcomm SDX65-MTP board.
>
> Signed-off-by: Kaushal Kumar <[email protected]>
> ---
> arch/arm/boot/dts/qcom-sdx65-mtp.dts | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> index 5c5fcb0..3628104 100644
> --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> @@ -72,6 +72,21 @@
> status = "ok";
> };
>
> +&qpic_nand {
Nodes need to be sorted in alphabetical order.
Thanks,
Mani
> + status = "ok";
> +
> + nand@0 {
> + reg = <0>;
> +
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> + nand-bus-width = <8>;
> + /* ico and efs2 partitions are secured */
> + secure-regions = /bits/ 64 <0x500000 0x500000
> + 0xa00000 0xb00000>;
> + };
> +};
> +
> &apps_rsc {
> pmx65-rpmh-regulators {
> compatible = "qcom,pmx65-rpmh-regulators";
> --
> 2.7.4
>