This series adds support for Output Prcoessing Module (OPE) module on
Tegra210 and later generations of SoCs. OPE is a client of AHUB and
it has sub blocks of PEQ (Parametric Equalizer) and MBDRC (Multi Band
Dynamic Range Compressor) for data processing.
An ASoC component is registered for OPE, which includes PEQ and MBDRC
functions as well. This can be plugged in audio path using ALSA mixer
controls. The series adds necessary binding documentaion, driver and
DT binding patches to enable OPE module on Jetson platforms.
Changelog
=========
v2 -> v3:
---------
* Drop "Device Tree Bindings" string from bindind doc titles for
OPE, PEQ and MBDRC.
v1 -> v2:
---------
* Use generic node names for OPE, PEQ and MBDRC devices. Update
binding doc and DT patches for this.
* Remove redundant nodename rule enforcement from
OPE, PEQ and MBDRC nodes. Update binding doc patch for this.
* Fix spaces before binding doc examples and remove '|'
from binding doc descriptions.
Sameer Pujar (6):
ASoC: tegra: Add binding doc for OPE module
ASoC: tegra: Add Tegra210 based OPE driver
ASoC: tegra: AHUB routes for OPE module
arm64: defconfig: Build Tegra OPE module
arm64: tegra: Add OPE device on Tegra210 and later
arm64: tegra: Enable OPE on various platforms
.../bindings/sound/nvidia,tegra210-ahub.yaml | 4 +
.../bindings/sound/nvidia,tegra210-mbdrc.yaml | 47 +
.../bindings/sound/nvidia,tegra210-ope.yaml | 87 ++
.../bindings/sound/nvidia,tegra210-peq.yaml | 48 +
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 43 +
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 23 +
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 43 +
.../arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 43 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 23 +
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 84 ++
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 84 ++
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 40 +
.../dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 43 +
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 23 +
arch/arm64/configs/defconfig | 1 +
sound/soc/tegra/Kconfig | 9 +
sound/soc/tegra/Makefile | 2 +
sound/soc/tegra/tegra210_ahub.c | 39 +-
sound/soc/tegra/tegra210_mbdrc.c | 1012 ++++++++++++++++++++
sound/soc/tegra/tegra210_mbdrc.h | 215 +++++
sound/soc/tegra/tegra210_ope.c | 419 ++++++++
sound/soc/tegra/tegra210_ope.h | 90 ++
sound/soc/tegra/tegra210_peq.c | 434 +++++++++
sound/soc/tegra/tegra210_peq.h | 56 ++
24 files changed, 2908 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/nvidia,tegra210-mbdrc.yaml
create mode 100644 Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml
create mode 100644 Documentation/devicetree/bindings/sound/nvidia,tegra210-peq.yaml
create mode 100644 sound/soc/tegra/tegra210_mbdrc.c
create mode 100644 sound/soc/tegra/tegra210_mbdrc.h
create mode 100644 sound/soc/tegra/tegra210_ope.c
create mode 100644 sound/soc/tegra/tegra210_ope.h
create mode 100644 sound/soc/tegra/tegra210_peq.c
create mode 100644 sound/soc/tegra/tegra210_peq.h
--
2.7.4
Add AHUB routes for OPE module. The OPE module can be plugged into audio
path as per the need. The routing controls can be used to setup the audio
path with OPE similar to the already existing routes. The support is added
on Tegra210 and later Tegra SoCs where OPE module is present.
Signed-off-by: Sameer Pujar <[email protected]>
---
sound/soc/tegra/tegra210_ahub.c | 39 +++++++++++++++++++++++++++++++++++----
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/sound/soc/tegra/tegra210_ahub.c b/sound/soc/tegra/tegra210_ahub.c
index e1f90da..b38d205 100644
--- a/sound/soc/tegra/tegra210_ahub.c
+++ b/sound/soc/tegra/tegra210_ahub.c
@@ -170,6 +170,11 @@ static struct snd_soc_dai_driver tegra210_ahub_dais[] = {
DAI(MIXER1 TX3),
DAI(MIXER1 TX4),
DAI(MIXER1 TX5),
+ /* XBAR -> OPE -> XBAR */
+ DAI(OPE1 RX),
+ DAI(OPE1 TX),
+ DAI(OPE2 RX),
+ DAI(OPE2 TX),
};
static struct snd_soc_dai_driver tegra186_ahub_dais[] = {
@@ -294,6 +299,9 @@ static struct snd_soc_dai_driver tegra186_ahub_dais[] = {
DAI(ASRC1 RX6),
DAI(ASRC1 TX6),
DAI(ASRC1 RX7),
+ /* XBAR -> OPE -> XBAR */
+ DAI(OPE1 RX),
+ DAI(OPE1 TX),
};
static const char * const tegra210_ahub_mux_texts[] = {
@@ -337,6 +345,8 @@ static const char * const tegra210_ahub_mux_texts[] = {
"MIXER1 TX3",
"MIXER1 TX4",
"MIXER1 TX5",
+ "OPE1",
+ "OPE2",
};
static const char * const tegra186_ahub_mux_texts[] = {
@@ -408,6 +418,7 @@ static const char * const tegra186_ahub_mux_texts[] = {
"ASRC1 TX4",
"ASRC1 TX5",
"ASRC1 TX6",
+ "OPE1",
};
static const unsigned int tegra210_ahub_mux_values[] = {
@@ -459,6 +470,9 @@ static const unsigned int tegra210_ahub_mux_values[] = {
MUX_VALUE(1, 2),
MUX_VALUE(1, 3),
MUX_VALUE(1, 4),
+ /* OPE */
+ MUX_VALUE(2, 0),
+ MUX_VALUE(2, 1),
};
static const unsigned int tegra186_ahub_mux_values[] = {
@@ -540,6 +554,8 @@ static const unsigned int tegra186_ahub_mux_values[] = {
MUX_VALUE(3, 27),
MUX_VALUE(3, 28),
MUX_VALUE(3, 29),
+ /* OPE */
+ MUX_VALUE(2, 0),
};
/* Controls for t210 */
@@ -584,6 +600,8 @@ MUX_ENUM_CTRL_DECL(t210_mixer17_tx, 0x26);
MUX_ENUM_CTRL_DECL(t210_mixer18_tx, 0x27);
MUX_ENUM_CTRL_DECL(t210_mixer19_tx, 0x28);
MUX_ENUM_CTRL_DECL(t210_mixer110_tx, 0x29);
+MUX_ENUM_CTRL_DECL(t210_ope1_tx, 0x40);
+MUX_ENUM_CTRL_DECL(t210_ope2_tx, 0x41);
/* Controls for t186 */
MUX_ENUM_CTRL_DECL_186(t186_admaif1_tx, 0x00);
@@ -657,6 +675,7 @@ MUX_ENUM_CTRL_DECL_186(t186_asrc14_tx, 0x6f);
MUX_ENUM_CTRL_DECL_186(t186_asrc15_tx, 0x70);
MUX_ENUM_CTRL_DECL_186(t186_asrc16_tx, 0x71);
MUX_ENUM_CTRL_DECL_186(t186_asrc17_tx, 0x72);
+MUX_ENUM_CTRL_DECL_186(t186_ope1_tx, 0x40);
/* Controls for t234 */
MUX_ENUM_CTRL_DECL_234(t234_mvc1_tx, 0x44);
@@ -758,6 +777,8 @@ static const struct snd_soc_dapm_widget tegra210_ahub_widgets[] = {
TX_WIDGETS("MIXER1 TX3"),
TX_WIDGETS("MIXER1 TX4"),
TX_WIDGETS("MIXER1 TX5"),
+ WIDGETS("OPE1", t210_ope1_tx),
+ WIDGETS("OPE2", t210_ope2_tx),
};
static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = {
@@ -867,6 +888,7 @@ static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = {
TX_WIDGETS("ASRC1 TX4"),
TX_WIDGETS("ASRC1 TX5"),
TX_WIDGETS("ASRC1 TX6"),
+ WIDGETS("OPE1", t186_ope1_tx),
};
static const struct snd_soc_dapm_widget tegra234_ahub_widgets[] = {
@@ -976,6 +998,7 @@ static const struct snd_soc_dapm_widget tegra234_ahub_widgets[] = {
TX_WIDGETS("ASRC1 TX4"),
TX_WIDGETS("ASRC1 TX5"),
TX_WIDGETS("ASRC1 TX6"),
+ WIDGETS("OPE1", t186_ope1_tx),
};
#define TEGRA_COMMON_MUX_ROUTES(name) \
@@ -1018,7 +1041,11 @@ static const struct snd_soc_dapm_widget tegra234_ahub_widgets[] = {
{ name " Mux", "MIXER1 TX2", "MIXER1 TX2 XBAR-RX" }, \
{ name " Mux", "MIXER1 TX3", "MIXER1 TX3 XBAR-RX" }, \
{ name " Mux", "MIXER1 TX4", "MIXER1 TX4 XBAR-RX" }, \
- { name " Mux", "MIXER1 TX5", "MIXER1 TX5 XBAR-RX" },
+ { name " Mux", "MIXER1 TX5", "MIXER1 TX5 XBAR-RX" }, \
+ { name " Mux", "OPE1", "OPE1 XBAR-RX" },
+
+#define TEGRA210_ONLY_MUX_ROUTES(name) \
+ { name " Mux", "OPE2", "OPE2 XBAR-RX" },
#define TEGRA186_ONLY_MUX_ROUTES(name) \
{ name " Mux", "ADMAIF11", "ADMAIF11 XBAR-RX" }, \
@@ -1050,10 +1077,11 @@ static const struct snd_soc_dapm_widget tegra234_ahub_widgets[] = {
{ name " Mux", "ASRC1 TX5", "ASRC1 TX5 XBAR-RX" }, \
{ name " Mux", "ASRC1 TX6", "ASRC1 TX6 XBAR-RX" },
-#define TEGRA210_MUX_ROUTES(name) \
- TEGRA_COMMON_MUX_ROUTES(name)
+#define TEGRA210_MUX_ROUTES(name) \
+ TEGRA_COMMON_MUX_ROUTES(name) \
+ TEGRA210_ONLY_MUX_ROUTES(name)
-#define TEGRA186_MUX_ROUTES(name) \
+#define TEGRA186_MUX_ROUTES(name) \
TEGRA_COMMON_MUX_ROUTES(name) \
TEGRA186_ONLY_MUX_ROUTES(name)
@@ -1121,6 +1149,8 @@ static const struct snd_soc_dapm_route tegra210_ahub_routes[] = {
TEGRA210_MUX_ROUTES("MIXER1 RX8")
TEGRA210_MUX_ROUTES("MIXER1 RX9")
TEGRA210_MUX_ROUTES("MIXER1 RX10")
+ TEGRA210_MUX_ROUTES("OPE1")
+ TEGRA210_MUX_ROUTES("OPE2")
};
static const struct snd_soc_dapm_route tegra186_ahub_routes[] = {
@@ -1215,6 +1245,7 @@ static const struct snd_soc_dapm_route tegra186_ahub_routes[] = {
TEGRA186_MUX_ROUTES("ASRC1 RX5")
TEGRA186_MUX_ROUTES("ASRC1 RX6")
TEGRA186_MUX_ROUTES("ASRC1 RX7")
+ TEGRA186_MUX_ROUTES("OPE1")
};
static const struct snd_soc_component_driver tegra210_ahub_component = {
--
2.7.4
Output Processing Engine (OPE) module is a client of AHUB on Tegra210
and later generations of Tegra SoCs. Enable the driver build to use
this in audio path.
Signed-off-by: Sameer Pujar <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7d11053..3e154cb 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -808,6 +808,7 @@ CONFIG_SND_SOC_TEGRA=m
CONFIG_SND_SOC_TEGRA210_AHUB=m
CONFIG_SND_SOC_TEGRA210_DMIC=m
CONFIG_SND_SOC_TEGRA210_I2S=m
+CONFIG_SND_SOC_TEGRA210_OPE=m
CONFIG_SND_SOC_TEGRA186_ASRC=m
CONFIG_SND_SOC_TEGRA186_DSPK=m
CONFIG_SND_SOC_TEGRA210_ADMAIF=m
--
2.7.4
Output Processing Engine (OPE) is a client of AHUB and is present on
Tegra210 and later generations of Tegra SoC. Add this device on the
relevant SoC DTSI files.
Signed-off-by: Sameer Pujar <[email protected]>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 23 ++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 23 ++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 40 ++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 23 ++++++++++++++++++
4 files changed, 109 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 0e9afc3..cd8c4f3 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -509,6 +509,29 @@
status = "disabled";
};
+ tegra_ope1: processing-engine@2908000 {
+ compatible = "nvidia,tegra186-ope",
+ "nvidia,tegra210-ope";
+ reg = <0x2908000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ sound-name-prefix = "OPE1";
+ status = "disabled";
+
+ equalizer@2908100 {
+ compatible = "nvidia,tegra186-peq",
+ "nvidia,tegra210-peq";
+ reg = <0x2908100 0x100>;
+ };
+
+ dynamic-range-compressor@2908200 {
+ compatible = "nvidia,tegra186-mbdrc",
+ "nvidia,tegra210-mbdrc";
+ reg = <0x2908200 0x200>;
+ };
+ };
+
tegra_amixer: amixer@290bb00 {
compatible = "nvidia,tegra186-amixer",
"nvidia,tegra210-amixer";
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index d1f8248..e65d1b0 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -562,6 +562,29 @@
status = "disabled";
};
+ tegra_ope1: processing-engine@2908000 {
+ compatible = "nvidia,tegra194-ope",
+ "nvidia,tegra210-ope";
+ reg = <0x2908000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ sound-name-prefix = "OPE1";
+ status = "disabled";
+
+ equalizer@2908100 {
+ compatible = "nvidia,tegra194-peq",
+ "nvidia,tegra210-peq";
+ reg = <0x2908100 0x100>;
+ };
+
+ dynamic-range-compressor@2908200 {
+ compatible = "nvidia,tegra194-mbdrc",
+ "nvidia,tegra210-mbdrc";
+ reg = <0x2908200 0x200>;
+ };
+ };
+
tegra_amixer: amixer@290bb00 {
compatible = "nvidia,tegra194-amixer",
"nvidia,tegra210-amixer";
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 4f0e51f..04383a1 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1723,6 +1723,46 @@
status = "disabled";
};
+ tegra_ope1: processing-engine@702d8000 {
+ compatible = "nvidia,tegra210-ope";
+ reg = <0x702d8000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ sound-name-prefix = "OPE1";
+ status = "disabled";
+
+ equalizer@702d8100 {
+ compatible = "nvidia,tegra210-peq";
+ reg = <0x702d8100 0x100>;
+ };
+
+ dynamic-range-compressor@702d8200 {
+ compatible = "nvidia,tegra210-mbdrc";
+ reg = <0x702d8200 0x200>;
+ };
+ };
+
+ tegra_ope2: processing-engine@702d8400 {
+ compatible = "nvidia,tegra210-ope";
+ reg = <0x702d8400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ sound-name-prefix = "OPE2";
+ status = "disabled";
+
+ equalizer@702d8500 {
+ compatible = "nvidia,tegra210-peq";
+ reg = <0x702d8500 0x100>;
+ };
+
+ dynamic-range-compressor@702d8600 {
+ compatible = "nvidia,tegra210-mbdrc";
+ reg = <0x702d8600 0x200>;
+ };
+ };
+
tegra_amixer: amixer@702dbb00 {
compatible = "nvidia,tegra210-amixer";
reg = <0x702dbb00 0x800>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index cb3af53..7e07684 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -304,6 +304,29 @@
status = "disabled";
};
+ tegra_ope1: processing-engine@2908000 {
+ compatible = "nvidia,tegra234-ope",
+ "nvidia,tegra210-ope";
+ reg = <0x2908000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ sound-name-prefix = "OPE1";
+ status = "disabled";
+
+ equalizer@2908100 {
+ compatible = "nvidia,tegra234-peq",
+ "nvidia,tegra210-peq";
+ reg = <0x2908100 0x100>;
+ };
+
+ dynamic-range-compressor@2908200 {
+ compatible = "nvidia,tegra234-mbdrc",
+ "nvidia,tegra210-mbdrc";
+ reg = <0x2908200 0x200>;
+ };
+ };
+
tegra_mvc1: mvc@290a000 {
compatible = "nvidia,tegra234-mvc",
"nvidia,tegra210-mvc";
--
2.7.4
Enable OPE module usage on various Jetson platforms. This can be plugged
into an audio path using ALSA mixer controls. Add audio-graph-port binding
to use OPE device with generic audio-graph based sound card.
Signed-off-by: Sameer Pujar <[email protected]>
---
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 43 +++++++++++
arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 43 +++++++++++
.../arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 43 +++++++++++
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 84 ++++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 84 ++++++++++++++++++++++
.../dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 43 +++++++++++
6 files changed, 340 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index 70737a0..bd18977 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -915,6 +915,22 @@
remote-endpoint = <&asrc_in7_ep>;
};
};
+
+ xbar_ope1_in_port: port@70 {
+ reg = <0x70>;
+
+ xbar_ope1_in_ep: endpoint {
+ remote-endpoint = <&ope1_cif_in_ep>;
+ };
+ };
+
+ port@71 {
+ reg = <0x71>;
+
+ xbar_ope1_out_ep: endpoint {
+ remote-endpoint = <&ope1_cif_out_ep>;
+ };
+ };
};
admaif@290f000 {
@@ -1911,6 +1927,31 @@
};
};
+ processing-engine@2908000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ ope1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_in_ep>;
+ };
+ };
+
+ ope1_out_port: port@1 {
+ reg = <0x1>;
+
+ ope1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_out_ep>;
+ };
+ };
+ };
+ };
+
amixer@290bb00 {
status = "okay";
@@ -2552,6 +2593,7 @@
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
+ <&xbar_ope1_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@@ -2571,6 +2613,7 @@
<&mixer_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+ <&ope1_out_port>,
/* I/O */
<&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
<&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
index bce518a..fafd707 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -868,6 +868,22 @@
remote-endpoint = <&asrc_in7_ep>;
};
};
+
+ xbar_ope1_in_port: port@70 {
+ reg = <0x70>;
+
+ xbar_ope1_in_ep: endpoint {
+ remote-endpoint = <&ope1_cif_in_ep>;
+ };
+ };
+
+ port@71 {
+ reg = <0x71>;
+
+ xbar_ope1_out_ep: endpoint {
+ remote-endpoint = <&ope1_cif_out_ep>;
+ };
+ };
};
admaif@290f000 {
@@ -1710,6 +1726,31 @@
};
};
+ processing-engine@2908000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ ope1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_in_ep>;
+ };
+ };
+
+ ope1_out_port: port@1 {
+ reg = <0x1>;
+
+ ope1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_out_ep>;
+ };
+ };
+ };
+ };
+
amixer@290bb00 {
status = "okay";
@@ -2273,6 +2314,7 @@
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
+ <&xbar_ope1_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@@ -2291,6 +2333,7 @@
<&mixer_out4_port>, <&mixer_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+ <&ope1_out_port>,
/* BE I/O Ports */
<&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
<&dmic3_port>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
index 7acc32d..4cee935 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi
@@ -878,6 +878,22 @@
remote-endpoint = <&asrc_in7_ep>;
};
};
+
+ xbar_ope1_in_port: port@70 {
+ reg = <0x70>;
+
+ xbar_ope1_in_ep: endpoint {
+ remote-endpoint = <&ope1_cif_in_ep>;
+ };
+ };
+
+ port@71 {
+ reg = <0x71>;
+
+ xbar_ope1_out_ep: endpoint {
+ remote-endpoint = <&ope1_cif_out_ep>;
+ };
+ };
};
admaif@290f000 {
@@ -1770,6 +1786,31 @@
};
};
+ processing-engine@2908000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ ope1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_in_ep>;
+ };
+ };
+
+ ope1_out_port: port@1 {
+ reg = <0x1>;
+
+ ope1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_out_ep>;
+ };
+ };
+ };
+ };
+
amixer@290bb00 {
status = "okay";
@@ -2323,6 +2364,7 @@
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
+ <&xbar_ope1_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@@ -2342,6 +2384,7 @@
<&mixer_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+ <&ope1_out_port>,
/* BE I/O Ports */
<&i2s3_port>, <&i2s5_port>,
<&dmic1_port>, <&dmic2_port>, <&dmic4_port>,
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index 328fbfe..1e26ca9 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -682,6 +682,56 @@
};
};
+ processing-engine@702d8000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ ope1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_in_ep>;
+ };
+ };
+
+ ope1_out_port: port@1 {
+ reg = <0x1>;
+
+ ope1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_out_ep>;
+ };
+ };
+ };
+ };
+
+ processing-engine@702d8400 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ ope2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope2_in_ep>;
+ };
+ };
+
+ ope2_out_port: port@1 {
+ reg = <0x1>;
+
+ ope2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope2_out_ep>;
+ };
+ };
+ };
+ };
+
amixer@702dbb00 {
status = "okay";
@@ -1251,6 +1301,38 @@
remote-endpoint = <&mixer_out5_ep>;
};
};
+
+ xbar_ope1_in_port: port@41 {
+ reg = <0x41>;
+
+ xbar_ope1_in_ep: endpoint {
+ remote-endpoint = <&ope1_cif_in_ep>;
+ };
+ };
+
+ port@42 {
+ reg = <0x42>;
+
+ xbar_ope1_out_ep: endpoint {
+ remote-endpoint = <&ope1_cif_out_ep>;
+ };
+ };
+
+ xbar_ope2_in_port: port@43 {
+ reg = <0x43>;
+
+ xbar_ope2_in_ep: endpoint {
+ remote-endpoint = <&ope2_cif_in_ep>;
+ };
+ };
+
+ port@44 {
+ reg = <0x44>;
+
+ xbar_ope2_out_ep: endpoint {
+ remote-endpoint = <&ope2_cif_out_ep>;
+ };
+ };
};
};
};
@@ -1281,6 +1363,7 @@
<&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
<&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
<&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
+ <&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@@ -1293,6 +1376,7 @@
<&mixer_out1_port>, <&mixer_out2_port>,
<&mixer_out3_port>, <&mixer_out4_port>,
<&mixer_out5_port>,
+ <&ope1_out_port>, <&ope2_out_port>,
/* I/O DAP Ports */
<&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
<&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
index 746bd52..749b44c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
@@ -1074,6 +1074,56 @@
};
};
+ processing-engine@702d8000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ ope1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_in_ep>;
+ };
+ };
+
+ ope1_out_port: port@1 {
+ reg = <0x1>;
+
+ ope1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_out_ep>;
+ };
+ };
+ };
+ };
+
+ processing-engine@702d8400 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ ope2_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope2_in_ep>;
+ };
+ };
+
+ ope2_out_port: port@1 {
+ reg = <0x1>;
+
+ ope2_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope2_out_ep>;
+ };
+ };
+ };
+ };
+
amixer@702dbb00 {
status = "okay";
@@ -1611,6 +1661,38 @@
remote-endpoint = <&mixer_out5_ep>;
};
};
+
+ xbar_ope1_in_port: port@41 {
+ reg = <0x41>;
+
+ xbar_ope1_in_ep: endpoint {
+ remote-endpoint = <&ope1_cif_in_ep>;
+ };
+ };
+
+ port@42 {
+ reg = <0x42>;
+
+ xbar_ope1_out_ep: endpoint {
+ remote-endpoint = <&ope1_cif_out_ep>;
+ };
+ };
+
+ xbar_ope2_in_port: port@43 {
+ reg = <0x43>;
+
+ xbar_ope2_in_ep: endpoint {
+ remote-endpoint = <&ope2_cif_in_ep>;
+ };
+ };
+
+ port@44 {
+ reg = <0x44>;
+
+ xbar_ope2_out_ep: endpoint {
+ remote-endpoint = <&ope2_cif_out_ep>;
+ };
+ };
};
};
};
@@ -1884,6 +1966,7 @@
<&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
<&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
<&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
+ <&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@@ -1896,6 +1979,7 @@
<&mixer_out1_port>, <&mixer_out2_port>,
<&mixer_out3_port>, <&mixer_out4_port>,
<&mixer_out5_port>,
+ <&ope1_out_port>, <&ope2_out_port>,
/* I/O DAP Ports */
<&i2s3_port>, <&i2s4_port>,
<&dmic1_port>, <&dmic2_port>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
index eaf1994..3f6c399 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
@@ -867,6 +867,22 @@
remote-endpoint = <&asrc_in7_ep>;
};
};
+
+ xbar_ope1_in_port: port@70 {
+ reg = <0x70>;
+
+ xbar_ope1_in_ep: endpoint {
+ remote-endpoint = <&ope1_cif_in_ep>;
+ };
+ };
+
+ port@71 {
+ reg = <0x71>;
+
+ xbar_ope1_out_ep: endpoint {
+ remote-endpoint = <&ope1_cif_out_ep>;
+ };
+ };
};
i2s@2901000 {
@@ -1490,6 +1506,31 @@
};
};
+ processing-engine@2908000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ ope1_cif_in_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_in_ep>;
+ };
+ };
+
+ ope1_out_port: port@1 {
+ reg = <0x1>;
+
+ ope1_cif_out_ep: endpoint {
+ remote-endpoint = <&xbar_ope1_out_ep>;
+ };
+ };
+ };
+ };
+
mvc@290a000 {
status = "okay";
@@ -2044,6 +2085,7 @@
<&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
<&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
<&xbar_asrc_in7_port>,
+ <&xbar_ope1_in_port>,
/* HW accelerators */
<&sfc1_out_port>, <&sfc2_out_port>,
<&sfc3_out_port>, <&sfc4_out_port>,
@@ -2062,6 +2104,7 @@
<&mix_out4_port>, <&mix_out5_port>,
<&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
<&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+ <&ope1_out_port>,
/* BE I/O Ports */
<&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
<&dmic3_port>;
--
2.7.4