2022-06-01 20:34:35

by Conor Dooley

[permalink] [raw]
Subject: [PATCH v5 0/2] rtc: microchip: Add driver for PolarFire SoC

Hey all,
This is technically a v5 of [0], although a fair bit of time has
passed since then. In the meantime I upstreamed the dt-binding, which
was in the v1, and this patch depends on the fixes to the dt-binding
and device tree etc which landed in v5.18-rc5.

The driver is quite substantially rewritten from the v1, as you wanted
it to be switched to "binary" rather than calendar mode - so hopefully I
have satisfied your concerns with the original driver. Specifically you
had an significant issue with the counter being reset on startup & that
is no longer the case.

Thanks,
Conor.

Changes since v4:
- replace duplicate define of BIT(6) with the missing BIT(7) define
- remove duplicate read of the mode register in mpfs_rtc_readalarm()
- simplify if (mode & MODE_WAKE_EN) to an assignment
- replace (potentially) infinite wait with read_poll_timeout

Changes since v3:
- invert read order of datetime registers so that they are properly
aligned. reads of the upper register are aligned to the last read
of the lower register
- move wakeup_irq out of mpfs_rtc_dev & into probe
- removed range_min since it is not set & implicity zero anyway
- rewrote the remove function to not call mpfs_rtc_alarm_irq_enable(,0)

Changes from v2:
- move prescaler out of mpfs_rtc_dev & into probe

Changes from v1:
- remove duplicate and unused defines
- remove oneline mpfs_rtc_set_prescaler function
- dont unconditionally turn off the rtc in the init function
- dont reset the rtc when init is run.
- dont disable the alarm when we boot
- use binary, not calendar mode
- delete mpfs_rtc_init & set prescale in probe
- use dev_pm_set_wake_irq rather than writing suspend/resume functions
- delete calendar mode only register defines
- since using binary mode, set range min to zero
- set range max to max alarm value (is this acceptable?)
- added a MAINTAINERS entry: when v1 was submitted there was nothing to
add to, but there is now.

[0] https://lore.kernel.org/linux-rtc/[email protected]/


Conor Dooley (2):
rtc: Add driver for Microchip PolarFire SoC
MAINTAINERS: add PolarFire SoC's RTC

MAINTAINERS | 1 +
drivers/rtc/Kconfig | 10 ++
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-mpfs.c | 326 +++++++++++++++++++++++++++++++++++++++++
4 files changed, 338 insertions(+)
create mode 100644 drivers/rtc/rtc-mpfs.c


base-commit: c5eb0a61238dd6faf37f58c9ce61c9980aaffd7a
--
2.36.1



2022-06-01 21:22:41

by Conor Dooley

[permalink] [raw]
Subject: [PATCH v5 2/2] MAINTAINERS: add PolarFire SoC's RTC

Add an entry for PolarFire SoC's RTC drver to the existing support
for PolarFire SoC.

Signed-off-by: Conor Dooley <[email protected]>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index e8c52d0192a6..625d735f6a24 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16952,6 +16952,7 @@ L: [email protected]
S: Supported
F: arch/riscv/boot/dts/microchip/
F: drivers/mailbox/mailbox-mpfs.c
+F: drivers/rtc/rtc-mpfs.c
F: drivers/soc/microchip/
F: include/soc/microchip/mpfs.h

--
2.36.1


2022-06-24 19:48:57

by Alexandre Belloni

[permalink] [raw]
Subject: Re: [PATCH v5 0/2] rtc: microchip: Add driver for PolarFire SoC

On Wed, 1 Jun 2022 13:33:19 +0100, Conor Dooley wrote:
> Hey all,
> This is technically a v5 of [0], although a fair bit of time has
> passed since then. In the meantime I upstreamed the dt-binding, which
> was in the v1, and this patch depends on the fixes to the dt-binding
> and device tree etc which landed in v5.18-rc5.
>
> The driver is quite substantially rewritten from the v1, as you wanted
> it to be switched to "binary" rather than calendar mode - so hopefully I
> have satisfied your concerns with the original driver. Specifically you
> had an significant issue with the counter being reset on startup & that
> is no longer the case.
>
> [...]

Applied, thanks!

[1/2] rtc: Add driver for Microchip PolarFire SoC
commit: 0b31d703598dc1993867597bbd45e87d824fc427
[2/2] MAINTAINERS: add PolarFire SoC's RTC
commit: 1bdb08c180e8556d3d4cef844ea0f0bae79bb95d

Best regards,
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com