This is a respin of "Multiple addition to ipq8064 dtsi" series
with major changes and some commit removed.
This series try to add some of the missing bindings for ipq806x.
This still lacks of the cpu bindings and all the bindings required
to scale cpu clk or L2. These will come later as the driver and
documentation require some changes.
So for now we try to add bindings that can directly applied without
making changes to any drivers.
Changes:
v2:
- Dropped "add sic non secure node for ipq8064" (no user found)
- Dropped "add smem node for ipq8064" (require changes to the driver
to remove syscon node and use regs directly, will be added in a
different series)
- Dropped "fix dtc warning for missing #address-cells for ipq8064" (
doesn't actually fix any warning)
- Changed "enable usb phy by default for ipq8064" to disable usb phy
by default
- Reworked rpm smb208 declaration to a saparate dtsi
- Fixed order with compatible-reg-status
- Squashed "remove redundant binding from ipq8064 rb3011 dts" with
"add multiple missing pin definition for ipq8064" to prevent dtc
error.
- Add review tag for snps patch
Changes from "Multiple addition to ipq8064 dtsi":
v3:
- Fix error in rb3011 dts
- Add tested-by tag on the entire series
v2:
- Added missing patch
- Added additional gsbi6 spi
- Added extra description for L2 cache opp
- Fxied smb208 enabled by default that is problematic for rb3011 devices
Christian Marangi (8):
ARM: dts: qcom: add multiple missing pin definition for ipq8064
ARM: dts: qcom: add gsbi6 missing definition for ipq8064
ARM: dts: qcom: add specific ipq8064 dtsi with smb208 rpm regulators
ARM: dts: qcom: add missing snps,dwmac compatible for gmac ipq8064
ARM: dts: qcom: disable usb phy by default for ipq8064
ARM: dts: qcom: reduce pci IO size to 64K for ipq8064
ARM: dts: qcom: fix and add some missing gsbi node for ipq8064
ARM: dts: qcom: add speedbin efuse nvmem node
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 6 -
arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 9 --
arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi | 37 +++++
arch/arm/boot/dts/qcom-ipq8064.dtsi | 150 +++++++++++++++++++--
4 files changed, 179 insertions(+), 23 deletions(-)
create mode 100644 arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
--
2.36.1
Add missing definition for mdio0 pins used for gpio-bitbang driver,i2c4
pins and rgmii2 pins for ipq8064.
Drop i2c4_pins node from ipq8064-ap148 dts as it's now moved to ipq8064
dtsi.
Drop mdio0_pins node from ipq8064-rb3011 dts as it's now moved to
ipq8064 dtsi.
Signed-off-by: Christian Marangi <[email protected]>
Tested-by: Jonathan McDowell <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 6 -----
arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 9 -------
arch/arm/boot/dts/qcom-ipq8064.dtsi | 32 +++++++++++++++++++++++
3 files changed, 32 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index b63d01d10189..a654d3c22c4f 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -7,12 +7,6 @@ / {
soc {
pinmux@800000 {
- i2c4_pins: i2c4_pinmux {
- pins = "gpio12", "gpio13";
- function = "gsbi4";
- bias-disable;
- };
-
buttons_pins: buttons_pins {
mux {
pins = "gpio54", "gpio65";
diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
index 9034f00f2bd8..5a65cce2500c 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
@@ -307,15 +307,6 @@ mux {
};
};
- mdio0_pins: mdio0_pins {
- mux {
- pins = "gpio0", "gpio1";
- function = "gpio";
- drive-strength = <8>;
- bias-disable;
- };
- };
-
mdio1_pins: mdio1_pins {
mux {
pins = "gpio10", "gpio11";
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 4b475d98343c..bc9987c841d0 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -382,6 +382,13 @@ mux {
};
};
+ i2c4_pins: i2c4-default {
+ pins = "gpio12", "gpio13";
+ function = "gsbi4";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
@@ -424,6 +431,8 @@ mux {
pullups {
pins = "gpio39";
+ function = "nand";
+ drive-strength = <10>;
bias-pull-up;
};
@@ -431,9 +440,32 @@ hold {
pins = "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45",
"gpio46", "gpio47";
+ function = "nand";
+ drive-strength = <10>;
bias-bus-hold;
};
};
+
+ mdio0_pins: mdio0-pins {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ rgmii2_pins: rgmii2-pins {
+ mux {
+ pins = "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31", "gpio32",
+ "gpio51", "gpio52", "gpio59",
+ "gpio60", "gpio61", "gpio62";
+ function = "rgmii2";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
};
intc: interrupt-controller@2000000 {
--
2.36.1
The current value for pci IO is problematic for ath10k wifi card
commonly connected to ipq8064 SoC.
The current value is probably a typo and is actually uncommon to find
1MB IO space even on a x86 arch. Also with recent changes to the pci
driver, pci1 and pci2 now fails to function as any connected device
fails any reg read/write. Reduce this to 64K as it should be more than
enough and 3 * 64K of total IO space doesn't exceed the IO_SPACE_LIMIT
hardcoded for the ARM arch.
Signed-off-by: Christian Marangi <[email protected]>
Tested-by: Jonathan McDowell <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index e70167870476..8d2f7c8bf6ac 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -885,7 +885,7 @@ pcie0: pci@1b500000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
+ ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
@@ -936,7 +936,7 @@ pcie1: pci@1b700000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
+ ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
@@ -987,7 +987,7 @@ pcie2: pci@1b900000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
+ ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
--
2.36.1
Add some tag for gsbi to make them usable for ipq8064 SoC. Add missing
gsbi7 i2c node and gsbi1 node.
Signed-off-by: Christian Marangi <[email protected]>
Tested-by: Jonathan McDowell <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 54 ++++++++++++++++++++++++++++-
1 file changed, 53 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 8d2f7c8bf6ac..69cf664851c6 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -539,6 +539,44 @@ saw1: regulator@2099000 {
regulator;
};
+ gsbi1: gsbi@12440000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x12440000 0x100>;
+ cell-index = <1>;
+ clocks = <&gcc GSBI1_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+
+ status = "disabled";
+
+ gsbi1_serial: serial@12450000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x12450000 0x100>,
+ <0x12400000 0x03>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+
+ status = "disabled";
+ };
+
+ gsbi1_i2c: i2c@12460000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x12460000 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
gsbi2: gsbi@12480000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <2>;
@@ -562,7 +600,7 @@ gsbi2_serial: serial@12490000 {
status = "disabled";
};
- i2c@124a0000 {
+ gsbi2_i2c: i2c@124a0000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x124a0000 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
@@ -727,6 +765,20 @@ gsbi7_serial: serial@16640000 {
clock-names = "core", "iface";
status = "disabled";
};
+
+ gsbi7_i2c: i2c@16680000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16680000 0x1000>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
+ clock-names = "core", "iface";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
};
rng@1a500000 {
--
2.36.1
Add speedbin efuse nvmem binding needed for the opp table for the CPU
freqs.
Signed-off-by: Christian Marangi <[email protected]>
Tested-by: Jonathan McDowell <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 69cf664851c6..71572028bc36 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -854,6 +854,9 @@ qfprom: qfprom@700000 {
reg = <0x00700000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+ speedbin_efuse: speedbin@c0 {
+ reg = <0xc0 0x4>;
+ };
tsens_calib: calib@400 {
reg = <0x400 0xb>;
};
--
2.36.1
Disable usb phy by default. When the usb phy were pushed, half of them
were flagged as disabled by mistake.
Correctly disable all usb phy and enable them only if a device actually
use them.
Signed-off-by: Christian Marangi <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index a80090f5509e..e70167870476 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1188,6 +1188,8 @@ hs_phy_1: phy@110f8800 {
clocks = <&gcc USB30_1_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
+
+ status = "disabled";
};
ss_phy_1: phy@110f8830 {
@@ -1196,6 +1198,8 @@ ss_phy_1: phy@110f8830 {
clocks = <&gcc USB30_1_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
+
+ status = "disabled";
};
usb3_1: usb3@110f8800 {
--
2.36.1
Add speedbin efuse nvmem cell needed for the opp table for the CPU
freqs.
Signed-off-by: Christian Marangi <[email protected]>
Tested-by: Jonathan McDowell <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 69cf664851c6..71572028bc36 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -854,6 +854,9 @@ qfprom: qfprom@700000 {
reg = <0x00700000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+ speedbin_efuse: speedbin@c0 {
+ reg = <0xc0 0x4>;
+ };
tsens_calib: calib@400 {
reg = <0x400 0xb>;
};
--
2.36.1
Add missing snps,dwmac compatible for gmac ipq8064 dtsi.
Signed-off-by: Christian Marangi <[email protected]>
Tested-by: Jonathan McDowell <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 7cccfe99bf00..a80090f5509e 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1042,7 +1042,7 @@ stmmac_axi_setup: stmmac-axi-config {
gmac0: ethernet@37000000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37000000 0x200000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -1066,7 +1066,7 @@ gmac0: ethernet@37000000 {
gmac1: ethernet@37200000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -1090,7 +1090,7 @@ gmac1: ethernet@37200000 {
gmac2: ethernet@37400000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -1114,7 +1114,7 @@ gmac2: ethernet@37400000 {
gmac3: ethernet@37600000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37600000 0x200000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
--
2.36.1
Add gsbi6 missing definition for ipq8064.
Signed-off-by: Christian Marangi <[email protected]>
Tested-by: Jonathan McDowell <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 43 +++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index bc9987c841d0..7cccfe99bf00 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -663,6 +663,49 @@ spi@1a280000 {
};
};
+ gsbi6: gsbi@16500000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x16500000 0x100>;
+ cell-index = <6>;
+ clocks = <&gcc GSBI6_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+
+ status = "disabled";
+
+ gsbi6_i2c: i2c@16580000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16580000 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
+ clock-names = "core", "iface";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ gsbi6_spi: spi@16580000 {
+ compatible = "qcom,spi-qup-v1.1.1";
+ reg = <0x16580000 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
+ clock-names = "core", "iface";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
gsbi7: gsbi@16600000 {
status = "disabled";
compatible = "qcom,gsbi-v1.0.0";
--
2.36.1
Add specific ipq8064 dtsi with smb208 rpm regulators.
Qcom advise to use this configuration but it's not mandatory and OEM
can decide to implement their own regulators.
smb208 regulators are used to scale CPU voltage, L2 cache voltage and
Ubi32 cores.
There regulators are controlled by rpm and to correctly works gsbi4-i2c
require to be NEVER disabled or rpm will reject any regulator change
request.
Signed-off-by: Christian Marangi <[email protected]>
Tested-by: Jonathan McDowell <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi | 37 ++++++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
new file mode 100644
index 000000000000..ac9c44f0c164
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "qcom-ipq8064.dtsi"
+
+&rpm {
+ smb208_regulators: regulators {
+ compatible = "qcom,rpm-smb208-regulators";
+
+ smb208_s1a: s1a {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s1b: s1b {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2a: s2a {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2b: s2b {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+ };
+};
--
2.36.1
On Thu, Jul 07, 2022 at 03:09:42AM +0200, Christian Marangi wrote:
> Add speedbin efuse nvmem binding needed for the opp table for the CPU
> freqs.
>
Slipped while fixing commit description, pls ignore. Sorry.
--
Ansuel
On Wed 06 Jul 20:09 CDT 2022, Christian Marangi wrote:
> This is a respin of "Multiple addition to ipq8064 dtsi" series
> with major changes and some commit removed.
>
> This series try to add some of the missing bindings for ipq806x.
>
> This still lacks of the cpu bindings and all the bindings required
> to scale cpu clk or L2. These will come later as the driver and
> documentation require some changes.
>
> So for now we try to add bindings that can directly applied without
> making changes to any drivers.
>
> Changes:
> v2:
> - Dropped "add sic non secure node for ipq8064" (no user found)
> - Dropped "add smem node for ipq8064" (require changes to the driver
> to remove syscon node and use regs directly, will be added in a
> different series)
> - Dropped "fix dtc warning for missing #address-cells for ipq8064" (
> doesn't actually fix any warning)
> - Changed "enable usb phy by default for ipq8064" to disable usb phy
> by default
> - Reworked rpm smb208 declaration to a saparate dtsi
> - Fixed order with compatible-reg-status
> - Squashed "remove redundant binding from ipq8064 rb3011 dts" with
> "add multiple missing pin definition for ipq8064" to prevent dtc
> error.
> - Add review tag for snps patch
>
> Changes from "Multiple addition to ipq8064 dtsi":
> v3:
> - Fix error in rb3011 dts
> - Add tested-by tag on the entire series
> v2:
> - Added missing patch
> - Added additional gsbi6 spi
> - Added extra description for L2 cache opp
> - Fxied smb208 enabled by default that is problematic for rb3011 devices
>
> Christian Marangi (8):
> ARM: dts: qcom: add multiple missing pin definition for ipq8064
> ARM: dts: qcom: add gsbi6 missing definition for ipq8064
> ARM: dts: qcom: add specific ipq8064 dtsi with smb208 rpm regulators
> ARM: dts: qcom: add missing snps,dwmac compatible for gmac ipq8064
> ARM: dts: qcom: disable usb phy by default for ipq8064
> ARM: dts: qcom: reduce pci IO size to 64K for ipq8064
> ARM: dts: qcom: fix and add some missing gsbi node for ipq8064
> ARM: dts: qcom: add speedbin efuse nvmem node
Please prefix your ipa8064-specific patches with
"ARM: dts: qcom: ipq8064: ..."
It makes the git history easier to read, so I fixed it up while applying
these.
Thanks,
Bjorn
>
> arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 6 -
> arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 9 --
> arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi | 37 +++++
> arch/arm/boot/dts/qcom-ipq8064.dtsi | 150 +++++++++++++++++++--
> 4 files changed, 179 insertions(+), 23 deletions(-)
> create mode 100644 arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
>
> --
> 2.36.1
>
On Thu, 7 Jul 2022 03:09:34 +0200, Christian Marangi wrote:
> This is a respin of "Multiple addition to ipq8064 dtsi" series
> with major changes and some commit removed.
>
> This series try to add some of the missing bindings for ipq806x.
>
> This still lacks of the cpu bindings and all the bindings required
> to scale cpu clk or L2. These will come later as the driver and
> documentation require some changes.
>
> [...]
Applied, thanks!
[1/8] ARM: dts: qcom: add multiple missing pin definition for ipq8064
commit: 4af1defb305798d1a064a5ea0d0c9b30e5eee185
[2/8] ARM: dts: qcom: add gsbi6 missing definition for ipq8064
commit: d883a12a547b6d42e795ff3b5ac87cfd013b5423
[3/8] ARM: dts: qcom: add specific ipq8064 dtsi with smb208 rpm regulators
commit: 5c47a46d5e942ea6b041c8b7727b201817c1ff76
[4/8] ARM: dts: qcom: add missing snps,dwmac compatible for gmac ipq8064
commit: 0ce34e0c13e99c239cce6099f64b0e95697f36b1
[5/8] ARM: dts: qcom: disable usb phy by default for ipq8064
commit: d63d3124c0a5cdbe8b91d81b922fe56b2462e1b9
[6/8] ARM: dts: qcom: reduce pci IO size to 64K for ipq8064
commit: 8fafb7e5c041814876266259e5e439f93571dcef
[7/8] ARM: dts: qcom: fix and add some missing gsbi node for ipq8064
commit: 6c421a9c08286389bb331fe783e2625c9efcc187
[8/8] ARM: dts: qcom: add speedbin efuse nvmem node
commit: 7f5aecdd4ffcc018f73171bc0e028cd4e3361acd
Best regards,
--
Bjorn Andersson <[email protected]>
On Sat, Jul 16, 2022 at 09:46:23PM -0500, Bjorn Andersson wrote:
> On Wed 06 Jul 20:09 CDT 2022, Christian Marangi wrote:
>
> > This is a respin of "Multiple addition to ipq8064 dtsi" series
> > with major changes and some commit removed.
> >
> > This series try to add some of the missing bindings for ipq806x.
> >
> > This still lacks of the cpu bindings and all the bindings required
> > to scale cpu clk or L2. These will come later as the driver and
> > documentation require some changes.
> >
> > So for now we try to add bindings that can directly applied without
> > making changes to any drivers.
> >
> > Changes:
> > v2:
> > - Dropped "add sic non secure node for ipq8064" (no user found)
> > - Dropped "add smem node for ipq8064" (require changes to the driver
> > to remove syscon node and use regs directly, will be added in a
> > different series)
> > - Dropped "fix dtc warning for missing #address-cells for ipq8064" (
> > doesn't actually fix any warning)
> > - Changed "enable usb phy by default for ipq8064" to disable usb phy
> > by default
> > - Reworked rpm smb208 declaration to a saparate dtsi
> > - Fixed order with compatible-reg-status
> > - Squashed "remove redundant binding from ipq8064 rb3011 dts" with
> > "add multiple missing pin definition for ipq8064" to prevent dtc
> > error.
> > - Add review tag for snps patch
> >
> > Changes from "Multiple addition to ipq8064 dtsi":
> > v3:
> > - Fix error in rb3011 dts
> > - Add tested-by tag on the entire series
> > v2:
> > - Added missing patch
> > - Added additional gsbi6 spi
> > - Added extra description for L2 cache opp
> > - Fxied smb208 enabled by default that is problematic for rb3011 devices
> >
> > Christian Marangi (8):
> > ARM: dts: qcom: add multiple missing pin definition for ipq8064
> > ARM: dts: qcom: add gsbi6 missing definition for ipq8064
> > ARM: dts: qcom: add specific ipq8064 dtsi with smb208 rpm regulators
> > ARM: dts: qcom: add missing snps,dwmac compatible for gmac ipq8064
> > ARM: dts: qcom: disable usb phy by default for ipq8064
> > ARM: dts: qcom: reduce pci IO size to 64K for ipq8064
> > ARM: dts: qcom: fix and add some missing gsbi node for ipq8064
> > ARM: dts: qcom: add speedbin efuse nvmem node
>
> Please prefix your ipa8064-specific patches with
> "ARM: dts: qcom: ipq8064: ..."
>
> It makes the git history easier to read, so I fixed it up while applying
> these.
>
Oh ok! I wasn't aware of this tag looking at the old commits. Will do
that in the next commits.
> >
> > arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 6 -
> > arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 9 --
> > arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi | 37 +++++
> > arch/arm/boot/dts/qcom-ipq8064.dtsi | 150 +++++++++++++++++++--
> > 4 files changed, 179 insertions(+), 23 deletions(-)
> > create mode 100644 arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
> >
> > --
> > 2.36.1
> >
--
Ansuel