From: Conor Dooley <[email protected]>
Hey all,
Got a few fixes for PCI dt-bindings that I noticed after upgrading my
dt-schema to v2022.08.
Since all the dts patches are for "my" boards, I'll take them once the
bindings are approved. I added a pair of other dts changes to the series,
mostly for my own benefit in tracking what I need to apply that were
previously at [0] & [1].
Thanks,
Conor.
0 - https://lore.kernel.org/all/[email protected]/
1 - https://lore.kernel.org/all/[email protected]/
Changes since v2:
- fu740: make clock-names required
- mchp: add regex to clock names
- mchp: add a new patch adding dma-ranges as optional
Changes since v1:
- fu740: rewrite commit message
- mchp: rework clock-names as per rob's suggestion on IRC
- mchp: drop the "legacy" from the node name
- mchp: renemove the address translation property
- mchp: change the child node name in the dts rather than the binding
Conor Dooley (7):
dt-bindings: PCI: fu740-pci: fix missing clock-names
dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties
dt-bindings: PCI: microchip,pcie-host: fix missing dma-ranges
riscv: dts: microchip: mpfs: fix incorrect pcie child node name
riscv: dts: microchip: mpfs: remove ti,fifo-depth property
riscv: dts: microchip: mpfs: remove bogus card-detect-delay
riscv: dts: microchip: mpfs: remove pci axi address translation
property
.../bindings/pci/microchip,pcie-host.yaml | 31 +++++++++++++++++++
.../bindings/pci/sifive,fu740-pcie.yaml | 8 +++++
.../boot/dts/microchip/mpfs-icicle-kit.dts | 3 --
.../boot/dts/microchip/mpfs-polarberry.dts | 3 --
arch/riscv/boot/dts/microchip/mpfs.dtsi | 3 +-
5 files changed, 40 insertions(+), 8 deletions(-)
base-commit: 69dac8e431af26173ca0a1ebc87054e01c585bcc
--
2.37.1
From: Conor Dooley <[email protected]>
An AXI master address translation table property was inadvertently
added to the device tree & this was not caught by dtbs_check at the
time. Remove the property - it should not be in mpfs.dtsi anyway as
it would be more suitable in -fabric.dtsi nor does it actually apply
to the version of the reference design we are using for upstream.
Link: https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide # Section 1.3.3
Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Signed-off-by: Conor Dooley <[email protected]>
---
arch/riscv/boot/dts/microchip/mpfs.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index e69322f56516..a1176260086a 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -485,7 +485,6 @@ pcie: pcie@2000000000 {
ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
msi-parent = <&pcie>;
msi-controller;
- microchip,axi-m-atr0 = <0x10 0x0>;
status = "disabled";
pcie_intc: interrupt-controller {
#address-cells = <0>;
--
2.37.1
From: Conor Dooley <[email protected]>
Recent versions of dt-schema warn about unevaluatedProperties:
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected)
From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
The clocks are required to enable interfaces between the FPGA fabric
and the core complex, so add them to the binding.
Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding")
Signed-off-by: Conor Dooley <[email protected]>
---
dt-schema v2022.08 is required to replicate
---
.../bindings/pci/microchip,pcie-host.yaml | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
index edb4f81253c8..6fbe62f4da93 100644
--- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
@@ -25,6 +25,33 @@ properties:
- const: cfg
- const: apb
+ clocks:
+ description:
+ Fabric Interface Controllers, FICs, are the interface between the FPGA
+ fabric and the core complex on PolarFire SoC. The FICs require two clocks,
+ one from each side of the interface. The "FIC clocks" described by this
+ property are on the core complex side & communication through a FIC is not
+ possible unless it's corresponding clock is enabled. A clock must be
+ enabled for each of the interfaces the root port is connected through.
+ This could in theory be all 4 interfaces, one interface or any combination
+ in between.
+ minItems: 1
+ items:
+ - description: FIC0's clock
+ - description: FIC1's clock
+ - description: FIC2's clock
+ - description: FIC3's clock
+
+ clock-names:
+ description:
+ As any FIC connection combination is possible, the names should match the
+ order in the clocks property and take the form "ficN" where N is a number
+ 0-3
+ minItems: 1
+ maxItems: 4
+ items:
+ pattern: '^fic[0-3]$'
+
interrupts:
minItems: 1
items:
--
2.37.1
On Sat, 20 Aug 2022 00:14:11 +0100, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> Recent versions of dt-schema warn about unevaluatedProperties:
> arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'legacy-interrupt-controller', 'microchip,axi-m-atr0' were unexpected)
> From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
>
> The clocks are required to enable interfaces between the FPGA fabric
> and the core complex, so add them to the binding.
>
> Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding")
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> dt-schema v2022.08 is required to replicate
> ---
> .../bindings/pci/microchip,pcie-host.yaml | 27 +++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
Reviewed-by: Rob Herring <[email protected]>
On Sat, 20 Aug 2022 00:14:09 +0100, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> Hey all,
>
> Got a few fixes for PCI dt-bindings that I noticed after upgrading my
> dt-schema to v2022.08.
>
> [...]
Applied to pci/dt, thanks!
[1/7] dt-bindings: PCI: fu740-pci: fix missing clock-names
https://git.kernel.org/lpieralisi/pci/c/b408fad61d34
[2/7] dt-bindings: PCI: microchip,pcie-host: fix missing clocks properties
https://git.kernel.org/lpieralisi/pci/c/05a5741019a5
[3/7] dt-bindings: PCI: microchip,pcie-host: fix missing dma-ranges
https://git.kernel.org/lpieralisi/pci/c/1a7966b33b5b
Thanks,
Lorenzo
From: Conor Dooley <[email protected]>
On Sat, 20 Aug 2022 00:14:09 +0100, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> Hey all,
>
> Got a few fixes for PCI dt-bindings that I noticed after upgrading my
> dt-schema to v2022.08.
>
> [...]
Applied to dt-fixes, RISC-V should be back to 0 warnings in the next
linux-next. Thanks!
[4/7] riscv: dts: microchip: mpfs: fix incorrect pcie child node name
https://git.kernel.org/conor/c/3f67e6997603
[5/7] riscv: dts: microchip: mpfs: remove ti,fifo-depth property
https://git.kernel.org/conor/c/72a05748cbd2
[6/7] riscv: dts: microchip: mpfs: remove bogus card-detect-delay
https://git.kernel.org/conor/c/2b55915d27dc
[7/7] riscv: dts: microchip: mpfs: remove pci axi address translation property
https://git.kernel.org/conor/c/e4009c5fa77b
Thanks,
Conor.