Based on the 6.0-rc1 of the pci/next branch.
This series adds the i.MX8MP PCIe support and tested on i.MX8MP
EVK board when one PCIe NVME device is used.
- i.MX8MP PCIe has reversed initial PERST bit value refer to i.MX8MQ/i.MX8MM.
Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
- Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
And share as much as possible codes with i.MX8MM PCIe PHY.
- Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
driver.
Main changes v5-->v6:
- To avoid code duplication when find the gpr syscon regmap, add the
gpr compatible into the drvdata.
- Add one missing space before one curly brace in 3/7 of v5 series.
- 4/7 of v5 had been applied by Phillipp, thanks. For ease of tests, still
keep it in v6.
Main changes v4-->v5:
- Use Lucas' approach, let blk-ctrl driver do the hsio-mix resets.
- Fetch the iomuxc-gpr regmap by the different phandles.
Main changes v3-->v4:
- Regarding Phillipp's suggestions, add fix tag into the first commit.
- Add Reviewed and Tested tags.
Main changes v2-->v3:
- Fix the schema checking error in the PHY dt-binding patch.
- Inspired by Lucas, the PLL configurations might not required when
external OSC is used as PCIe referrence clock. It's true. Remove all
the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK board
with one NVME device is used.
- Drop the #4 patch of v2, since it had been applied by Rob.
Main changes v1-->v2:
- It's my fault forget including Vinod, re-send v2 after include Vinod
and [email protected].
- List the basements of this patch-set. The branch, codes changes and so on.
- Clean up some useless register and bit definitions in #3 patch.
Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 16 ++++++++--
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 53 +++++++++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 43 +++++++++++++++++++++++++
drivers/pci/controller/dwc/pci-imx6.c | 27 ++++++++++++++--
drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 143 +++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------------------
drivers/reset/reset-imx7.c | 1 +
drivers/soc/imx/imx8mp-blk-ctrl.c | 10 ++++++
7 files changed, 241 insertions(+), 52 deletions(-)
[PATCH v6 1/7] dt-binding: phy: Add iMX8MP PCIe PHY binding
[PATCH v6 2/7] arm64: dts: imx8mp: Add iMX8MP PCIe support
[PATCH v6 3/7] arm64: dts: imx8mp-evk: Add PCIe support
[PATCH v6 4/7] reset: imx7: Fix the iMX8MP PCIe PHY PERST support
[PATCH v6 5/7] soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets
[PATCH v6 6/7] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY
[PATCH v6 7/7] PCI: imx6: Add i.MX8MP PCIe support
Add i.MX8MP PCIe PHY binding.
On iMX8MM, the initialized default value of PERST bit(BIT3) of
SRC_PCIEPHY_RCR is 1b'1.
But i.MX8MP has one inversed default value 1b'0 of PERST bit.
And the PERST bit should be kept 1b'1 after power and clocks are stable.
So add one more PERST explicitly for i.MX8MP PCIe PHY.
Signed-off-by: Richard Zhu <[email protected]>
Tested-by: Marek Vasut <[email protected]>
Tested-by: Richard Leitner <[email protected]>
Tested-by: Alexander Stein <[email protected]>
---
.../bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
index b6421eedece3..692783c7fd69 100644
--- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
@@ -16,6 +16,7 @@ properties:
compatible:
enum:
- fsl,imx8mm-pcie-phy
+ - fsl,imx8mp-pcie-phy
reg:
maxItems: 1
@@ -28,11 +29,16 @@ properties:
- const: ref
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
reset-names:
- items:
- - const: pciephy
+ oneOf:
+ - items: # for iMX8MM
+ - const: pciephy
+ - items: # for IMX8MP
+ - const: pciephy
+ - const: perst
fsl,refclk-pad-mode:
description: |
@@ -60,6 +66,10 @@ properties:
description: A boolean property indicating the CLKREQ# signal is
not supported in the board design (optional)
+ power-domains:
+ description: PCIe PHY power domain (optional).
+ maxItems: 1
+
required:
- "#phy-cells"
- compatible
--
2.25.1
On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3)
of SRC_PCIEPHY_RCR is 1b'1.
But i.MX8MP has one inversed default value 1b'0 of PERST bit.
And the PERST bit should be kept 1b'1 after power and clocks are stable.
So fix the i.MX8MP PCIe PHY PERST support here.
Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")
Signed-off-by: Richard Zhu <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
Tested-by: Marek Vasut <[email protected]>
Tested-by: Richard Leitner <[email protected]>
Tested-by: Alexander Stein <[email protected]>
---
drivers/reset/reset-imx7.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 185a333df66c..d2408725eb2c 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -329,6 +329,7 @@ static int imx8mp_reset_set(struct reset_controller_dev *rcdev,
break;
case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
+ case IMX8MP_RESET_PCIEPHY_PERST:
value = assert ? 0 : bit;
break;
}
--
2.25.1
Am Donnerstag, dem 01.09.2022 um 12:02 +0800 schrieb Richard Zhu:
> Add i.MX8MP PCIe PHY binding.
> On iMX8MM, the initialized default value of PERST bit(BIT3) of
> SRC_PCIEPHY_RCR is 1b'1.
> But i.MX8MP has one inversed default value 1b'0 of PERST bit.
>
> And the PERST bit should be kept 1b'1 after power and clocks are stable.
> So add one more PERST explicitly for i.MX8MP PCIe PHY.
>
> Signed-off-by: Richard Zhu <[email protected]>
> Tested-by: Marek Vasut <[email protected]>
> Tested-by: Richard Leitner <[email protected]>
> Tested-by: Alexander Stein <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
> ---
> .../bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> index b6421eedece3..692783c7fd69 100644
> --- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> @@ -16,6 +16,7 @@ properties:
> compatible:
> enum:
> - fsl,imx8mm-pcie-phy
> + - fsl,imx8mp-pcie-phy
>
> reg:
> maxItems: 1
> @@ -28,11 +29,16 @@ properties:
> - const: ref
>
> resets:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
>
> reset-names:
> - items:
> - - const: pciephy
> + oneOf:
> + - items: # for iMX8MM
> + - const: pciephy
> + - items: # for IMX8MP
> + - const: pciephy
> + - const: perst
>
> fsl,refclk-pad-mode:
> description: |
> @@ -60,6 +66,10 @@ properties:
> description: A boolean property indicating the CLKREQ# signal is
> not supported in the board design (optional)
>
> + power-domains:
> + description: PCIe PHY power domain (optional).
> + maxItems: 1
> +
> required:
> - "#phy-cells"
> - compatible