2022-07-11 09:10:25

by Jayesh Choudhary

[permalink] [raw]
Subject: [PATCH v2 0/2] Enable SA2UL support on AM64X

This series enables sa2ul support for TI SoC AM64X.
It is based on another series posted by Suman Anna:
<https://lore.kernel.org/linux-arm-kernel/[email protected]/>

rng node has been disabled due to its indirect access from OP-TEE.

Since the sa2ul hardware is being used by OP-TEE as well,
it should be requested using shared TI-SCI flag. So the flag
has been changed from TI-SCI-EXCLUSIVE to TI-SCI-SHARED.

I have tried crypto tests on my local setup, and tcrypt and
self-tests are passing.

Changes from v1:
- disable rng node instead of dropping it

Peter Ujfalusi (1):
arm64: dts: ti: k3-am64-main: Enable crypto accelerator

Suman Anna (1):
arm64: dts: ti: k3-am64: Add SA2UL address space to Main CBASS ranges

arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 20 ++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am64.dtsi | 1 +
2 files changed, 21 insertions(+)

--
2.17.1


2022-07-11 09:11:08

by Jayesh Choudhary

[permalink] [raw]
Subject: [PATCH v2 1/2] arm64: dts: ti: k3-am64: Add SA2UL address space to Main CBASS ranges

From: Suman Anna <[email protected]>

Add the address space for the SA2UL in MAIN domain to the ranges property
of the cbass_main interconnect node so that the addresses within the
corresponding sram nodes and its children can be translated properly by
the relevant OF address API.

Signed-off-by: Suman Anna <[email protected]>
Signed-off-by: Jayesh Choudhary <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am64.dtsi | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
index 016dd8511ca6..c858725133af 100644
--- a/arch/arm64/boot/dts/ti/k3-am64.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
@@ -82,6 +82,7 @@
<0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
<0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
<0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
+ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA2_UL0 */
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
--
2.17.1

2022-08-30 14:25:49

by Kamlesh Gurudasani

[permalink] [raw]
Subject: Re: [PATCH v2 1/2] arm64: dts: ti: k3-am64: Add SA2UL address space to Main CBASS ranges

Jayesh Choudhary <[email protected]> writes:

> From: Suman Anna <[email protected]>
>
> Add the address space for the SA2UL in MAIN domain to the ranges property
> of the cbass_main interconnect node so that the addresses within the
> corresponding sram nodes and its children can be translated properly by
> the relevant OF address API.
>
> Signed-off-by: Suman Anna <[email protected]>
> Signed-off-by: Jayesh Choudhary <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-am64.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
> index 016dd8511ca6..c858725133af 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
> @@ -82,6 +82,7 @@
> <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
> <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
> <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
> + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA2_UL0 */
> <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
> <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
> <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */

Reviewed-by: Kamlesh Gurudasani <[email protected]>

2022-09-01 15:10:22

by Vignesh Raghavendra

[permalink] [raw]
Subject: Re: [PATCH v2 0/2] Enable SA2UL support on AM64X

Hi Jayesh Choudhary,

On Mon, 11 Jul 2022 14:27:41 +0530, Jayesh Choudhary wrote:
> This series enables sa2ul support for TI SoC AM64X.
> It is based on another series posted by Suman Anna:
> <https://lore.kernel.org/linux-arm-kernel/[email protected]/>
>
> rng node has been disabled due to its indirect access from OP-TEE.
>
> Since the sa2ul hardware is being used by OP-TEE as well,
> it should be requested using shared TI-SCI flag. So the flag
> has been changed from TI-SCI-EXCLUSIVE to TI-SCI-SHARED.
>
> [...]

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/2] arm64: dts: ti: k3-am64: Add SA2UL address space to Main CBASS ranges
commit: e66e5b2d7f43d92fffb940988ed2822a1b28143b
[2/2] arm64: dts: ti: k3-am64-main: Enable crypto accelerator
commit: e170ae6dd67a00f750996820d55b144c5189be66

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh