The devicetree documentation for the nand node requires the subnode be
called nand@ and no compatible is needed.
Signed-off-by: Luca Weiss <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
index 5a65cce2500c..86f895db9894 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
@@ -264,8 +264,7 @@ &hs_phy_1 {
&nand {
status = "okay";
- nandcs@0 {
- compatible = "qcom,nandcs";
+ nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
--
2.38.0
The compatible "qcom,arch-cache" for l2-cache does not exist, and all
other Qualcomm boards use just "cache" for it. Fix it.
Signed-off-by: Luca Weiss <[email protected]>
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index f2fb7c975af8..e910b1f7c9ed 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -72,7 +72,7 @@ cpu@3 {
};
L2: l2-cache {
- compatible = "qcom,arch-cache";
+ compatible = "cache";
cache-level = <2>;
qcom,saw = <&saw_l2>;
};
--
2.38.0
There's a typo missing the arm, prefix of arm,coresight-etb10. Fix it to
make devicetree validation happier.
Signed-off-by: Luca Weiss <[email protected]>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 942aa2278355..a39b940d5853 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1615,7 +1615,7 @@ wifi {
};
etb@1a01000 {
- compatible = "coresight-etb10", "arm,primecell";
+ compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x1a01000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
--
2.38.0
On 13.10.2022 21:06, Luca Weiss wrote:
> The devicetree documentation for the nand node requires the subnode be
> called nand@ and no compatible is needed.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
> index 5a65cce2500c..86f895db9894 100644
> --- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
> +++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
> @@ -264,8 +264,7 @@ &hs_phy_1 {
> &nand {
> status = "okay";
>
> - nandcs@0 {
> - compatible = "qcom,nandcs";
> + nand@0 {
> reg = <0>;
>
> nand-ecc-strength = <4>;
On 13.10.2022 21:06, Luca Weiss wrote:
> There's a typo missing the arm, prefix of arm,coresight-etb10. Fix it to
> make devicetree validation happier.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
> index 942aa2278355..a39b940d5853 100644
> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> @@ -1615,7 +1615,7 @@ wifi {
> };
>
> etb@1a01000 {
> - compatible = "coresight-etb10", "arm,primecell";
> + compatible = "arm,coresight-etb10", "arm,primecell";
> reg = <0x1a01000 0x1000>;
>
> clocks = <&rpmcc RPM_QDSS_CLK>;
On 13.10.2022 21:06, Luca Weiss wrote:
> The compatible "qcom,arch-cache" for l2-cache does not exist, and all
> other Qualcomm boards use just "cache" for it. Fix it.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> arch/arm/boot/dts/qcom-apq8084.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
> index f2fb7c975af8..e910b1f7c9ed 100644
> --- a/arch/arm/boot/dts/qcom-apq8084.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
> @@ -72,7 +72,7 @@ cpu@3 {
> };
>
> L2: l2-cache {
> - compatible = "qcom,arch-cache";
> + compatible = "cache";
> cache-level = <2>;
> qcom,saw = <&saw_l2>;
> };
On 13/10/2022 15:06, Luca Weiss wrote:
> There's a typo missing the arm, prefix of arm,coresight-etb10. Fix it to
> make devicetree validation happier.
>
Fixes: 7a5c275fd821 ("ARM: dts: qcom: Add apq8064 CoreSight components")
> Signed-off-by: Luca Weiss <[email protected]>
With fixes tag:
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 13/10/2022 15:06, Luca Weiss wrote:
> The compatible "qcom,arch-cache" for l2-cache does not exist, and all
> other Qualcomm boards use just "cache" for it. Fix it.
>
> Signed-off-by: Luca Weiss <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 13/10/2022 15:06, Luca Weiss wrote:
> The devicetree documentation for the nand node requires the subnode be
> called nand@ and no compatible is needed.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
> arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 3 +--
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Thu, 13 Oct 2022 21:06:55 +0200, Luca Weiss wrote:
> The devicetree documentation for the nand node requires the subnode be
> called nand@ and no compatible is needed.
>
>
Applied, thanks!
[1/3] ARM: dts: qcom: ipq8064-rb3011: fix nand node validation
commit: 6f917ec31d3eb0f2c657f36d299d39bd8d051e03
[2/3] ARM: dts: qcom: apq8084: fix compatible for l2-cache
commit: 891bcfe02470c79489987d643ba0010c0b16f896
[3/3] ARM: dts: qcom: apq8064: fix coresight compatible
commit: a42b1ee868361f1cb0492f1bdaefb43e0751e468
Best regards,
--
Bjorn Andersson <[email protected]>