Convert Qualcomm IPQ8074 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 181 ------------------
.../pinctrl/qcom,ipq8074-pinctrl.yaml | 135 +++++++++++++
2 files changed, 135 insertions(+), 181 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
deleted file mode 100644
index 7b151894f5a0..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
+++ /dev/null
@@ -1,181 +0,0 @@
-Qualcomm Technologies, Inc. IPQ8074 TLMM block
-
-This binding describes the Top Level Mode Multiplexer block found in the
-IPQ8074 platform.
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: must be "qcom,ipq8074-pinctrl"
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: the base address and size of the TLMM register space.
-
-- interrupts:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: should specify the TLMM summary IRQ.
-
-- interrupt-controller:
- Usage: required
- Value type: <none>
- Definition: identifies this node as an interrupt controller
-
-- #interrupt-cells:
- Usage: required
- Value type: <u32>
- Definition: must be 2. Specifying the pin number and flags, as defined
- in <dt-bindings/interrupt-controller/irq.h>
-
-- gpio-controller:
- Usage: required
- Value type: <none>
- Definition: identifies this node as a gpio controller
-
-- #gpio-cells:
- Usage: required
- Value type: <u32>
- Definition: must be 2. Specifying the pin number and flags, as defined
- in <dt-bindings/gpio/gpio.h>
-
-- gpio-ranges:
- Usage: required
- Definition: see ../gpio/gpio.txt
-
-- gpio-reserved-ranges:
- Usage: optional
- Definition: see ../gpio/gpio.txt
-
-Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
-a general description of GPIO and interrupt bindings.
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-The pin configuration nodes act as a container for an arbitrary number of
-subnodes. Each of these subnodes represents some desired configuration for a
-pin, a group, or a list of pins or groups. This configuration can include the
-mux function to select on those pin(s)/group(s), and various pin configuration
-parameters, such as pull-up, drive strength, etc.
-
-
-PIN CONFIGURATION NODES:
-
-The name of each subnode is not important; all subnodes should be enumerated
-and processed purely based on their content.
-
-Each subnode only affects those parameters that are explicitly listed. In
-other words, a subnode that lists a mux function but no pin configuration
-parameters implies no information about any pin configuration parameters.
-Similarly, a pin subnode that describes a pullup parameter implies no
-information about e.g. the mux function.
-
-
-The following generic properties as defined in pinctrl-bindings.txt are valid
-to specify in a pin configuration subnode:
-
-- pins:
- Usage: required
- Value type: <string-array>
- Definition: List of gpio pins affected by the properties specified in
- this subnode. Valid pins are:
- gpio0-gpio69
-
-- function:
- Usage: required
- Value type: <string>
- Definition: Specify the alternative function to be configured for the
- specified pins. Functions are only valid for gpio pins.
- Valid values are:
- atest_char, atest_char0, atest_char1, atest_char2,
- atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync,
- audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync,
- audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c,
- blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart,
- blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2,
- blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0,
- blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi,
- blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1,
- cxc0, cxc1, dbg_out, gcc_plltest, gcc_tlmm, gpio, ldo_en,
- ldo_update, led0, led1, led2, mac0_sa0, mac0_sa1, mac1_sa0,
- mac1_sa1, mac1_sa2, mac1_sa3, mac2_sa0, mac2_sa1, mdc,
- mdio, pcie0_clk, pcie0_rst, pcie0_wake, pcie1_clk,
- pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx, pcm_fsync,
- pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0, pta1_1,
- pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3,
- qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
- qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
- qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
- qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
- qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
- qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b,
- qpic, rx0, rx1, rx2, sd_card, sd_write, tsens_max, wci2a,
- wci2b, wci2c, wci2d
-
-- bias-disable:
- Usage: optional
- Value type: <none>
- Definition: The specified pins should be configured as no pull.
-
-- bias-pull-down:
- Usage: optional
- Value type: <none>
- Definition: The specified pins should be configured as pull down.
-
-- bias-pull-up:
- Usage: optional
- Value type: <none>
- Definition: The specified pins should be configured as pull up.
-
-- output-high:
- Usage: optional
- Value type: <none>
- Definition: The specified pins are configured in output mode, driven
- high.
-
-- output-low:
- Usage: optional
- Value type: <none>
- Definition: The specified pins are configured in output mode, driven
- low.
-
-- drive-strength:
- Usage: optional
- Value type: <u32>
- Definition: Selects the drive strength for the specified pins, in mA.
- Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
-
-Example:
-
- tlmm: pinctrl@1000000 {
- compatible = "qcom,ipq8074-pinctrl";
- reg = <0x1000000 0x300000>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&tlmm 0 0 70>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- uart2: uart2-default {
- mux {
- pins = "gpio23", "gpio24";
- function = "blsp4_uart1";
- };
-
- rx {
- pins = "gpio23";
- drive-strength = <4>;
- bias-disable;
- };
-
- tx {
- pins = "gpio24";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml
new file mode 100644
index 000000000000..c02dd2ad9b31
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8074-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ8074 TLMM pin controller
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+ - Krzysztof Kozlowski <[email protected]>
+
+description:
+ Top Level Mode Multiplexer pin controller in Qualcomm IPQ8074 SoC.
+
+properties:
+ compatible:
+ const: qcom,ipq8074-pinctrl
+
+ reg:
+ maxItems: 1
+
+ interrupts: true
+ interrupt-controller: true
+ "#interrupt-cells": true
+ gpio-controller: true
+ "#gpio-cells": true
+ gpio-ranges: true
+ wakeup-parent: true
+
+ gpio-reserved-ranges:
+ minItems: 1
+ maxItems: 35
+
+ gpio-line-names:
+ maxItems: 70
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-ipq8074-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-ipq8074-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-ipq8074-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ pattern: "^gpio([0-9]|[1-6][0-9]|70)$"
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ gpio, atest_char, atest_char0, atest_char1, atest_char2,
+ atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync,
+ audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync,
+ audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c,
+ blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart,
+ blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2,
+ blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0,
+ blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi,
+ blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1, cxc0,
+ cxc1, dbg_out, gcc_plltest, gcc_tlmm, ldo_en, ldo_update, led0,
+ led1, led2, mac0_sa0, mac0_sa1, mac1_sa0, mac1_sa1, mac1_sa2,
+ mac1_sa3, mac2_sa0, mac2_sa1, mdc, mdio, pcie0_clk, pcie0_rst,
+ pcie0_wake, pcie1_clk, pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx,
+ pcm_fsync, pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0,
+ pta1_1, pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3,
+ qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
+ qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
+ qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
+ qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,
+ qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
+ qdss_tracedata_b, qpic, rx0, rx1, rx2, sd_card, sd_write,
+ tsens_max, wci2a, wci2b, wci2c, wci2d ]
+
+ bias-pull-down: true
+ bias-pull-up: true
+ bias-disable: true
+ drive-strength: true
+ input-enable: true
+ output-high: true
+ output-low: true
+
+ required:
+ - pins
+
+ additionalProperties: false
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq8074-pinctrl";
+ reg = <0x01000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ gpio-ranges = <&tlmm 0 0 70>;
+ #gpio-cells = <0x2>;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+
+ serial4-state {
+ pins = "gpio23", "gpio24";
+ function = "blsp4_uart1";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
--
2.34.1
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index d3d9e7eb5837..363ccc272cf1 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -317,35 +317,35 @@ tlmm: pinctrl@1000000 {
interrupt-controller;
#interrupt-cells = <0x2>;
- serial_4_pins: serial4-pinmux {
+ serial_4_pins: serial4-state {
pins = "gpio23", "gpio24";
function = "blsp4_uart1";
drive-strength = <8>;
bias-disable;
};
- i2c_0_pins: i2c-0-pinmux {
+ i2c_0_pins: i2c-0-state {
pins = "gpio42", "gpio43";
function = "blsp1_i2c";
drive-strength = <8>;
bias-disable;
};
- spi_0_pins: spi-0-pins {
+ spi_0_pins: spi-0-state {
pins = "gpio38", "gpio39", "gpio40", "gpio41";
function = "blsp0_spi";
drive-strength = <8>;
bias-disable;
};
- hsuart_pins: hsuart-pins {
+ hsuart_pins: hsuart-state {
pins = "gpio46", "gpio47", "gpio48", "gpio49";
function = "blsp2_uart";
drive-strength = <8>;
bias-disable;
};
- qpic_pins: qpic-pins {
+ qpic_pins: qpic-state {
pins = "gpio1", "gpio3", "gpio4",
"gpio5", "gpio6", "gpio7",
"gpio8", "gpio10", "gpio11",
--
2.34.1
On 08/11/2022 15:23, Krzysztof Kozlowski wrote:
> DT schema expects TLMM pin configuration nodes to be named with
> '-state' suffix and their optional children with '-pins' suffix.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> index d3d9e7eb5837..363ccc272cf1 100644
> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> @@ -317,35 +317,35 @@ tlmm: pinctrl@1000000 {
> interrupt-controller;
> #interrupt-cells = <0x2>;
>
> - serial_4_pins: serial4-pinmux {
> + serial_4_pins: serial4-state {
> pins = "gpio23", "gpio24";
> function = "blsp4_uart1";
> drive-strength = <8>;
> bias-disable;
> };
>
> - i2c_0_pins: i2c-0-pinmux {
> + i2c_0_pins: i2c-0-state {
> pins = "gpio42", "gpio43";
> function = "blsp1_i2c";
> drive-strength = <8>;
> bias-disable;
> };
>
> - spi_0_pins: spi-0-pins {
> + spi_0_pins: spi-0-state {
> pins = "gpio38", "gpio39", "gpio40", "gpio41";
> function = "blsp0_spi";
> drive-strength = <8>;
> bias-disable;
> };
>
> - hsuart_pins: hsuart-pins {
> + hsuart_pins: hsuart-state {
> pins = "gpio46", "gpio47", "gpio48", "gpio49";
> function = "blsp2_uart";
> drive-strength = <8>;
> bias-disable;
> };
>
> - qpic_pins: qpic-pins {
> + qpic_pins: qpic-state {
> pins = "gpio1", "gpio3", "gpio4",
> "gpio5", "gpio6", "gpio7",
> "gpio8", "gpio10", "gpio11",
On Tue, Nov 8, 2022 at 3:24 PM Krzysztof Kozlowski
<[email protected]> wrote:
> Convert Qualcomm IPQ8074 pin controller bindings to DT schema. Keep the
> parsing of pin configuration subnodes consistent with other Qualcomm
> schemas (children named with '-state' suffix, their children with
> '-pins').
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Tue, Nov 08, 2022 at 03:23:56PM +0100, Krzysztof Kozlowski wrote:
> Convert Qualcomm IPQ8074 pin controller bindings to DT schema. Keep the
> parsing of pin configuration subnodes consistent with other Qualcomm
> schemas (children named with '-state' suffix, their children with
> '-pins').
>
Reviewed-by: Bjorn Andersson <[email protected]>
Regards,
Bjorn
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 181 ------------------
> .../pinctrl/qcom,ipq8074-pinctrl.yaml | 135 +++++++++++++
> 2 files changed, 135 insertions(+), 181 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
> deleted file mode 100644
> index 7b151894f5a0..000000000000
> --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
> +++ /dev/null
> @@ -1,181 +0,0 @@
> -Qualcomm Technologies, Inc. IPQ8074 TLMM block
> -
> -This binding describes the Top Level Mode Multiplexer block found in the
> -IPQ8074 platform.
> -
> -- compatible:
> - Usage: required
> - Value type: <string>
> - Definition: must be "qcom,ipq8074-pinctrl"
> -
> -- reg:
> - Usage: required
> - Value type: <prop-encoded-array>
> - Definition: the base address and size of the TLMM register space.
> -
> -- interrupts:
> - Usage: required
> - Value type: <prop-encoded-array>
> - Definition: should specify the TLMM summary IRQ.
> -
> -- interrupt-controller:
> - Usage: required
> - Value type: <none>
> - Definition: identifies this node as an interrupt controller
> -
> -- #interrupt-cells:
> - Usage: required
> - Value type: <u32>
> - Definition: must be 2. Specifying the pin number and flags, as defined
> - in <dt-bindings/interrupt-controller/irq.h>
> -
> -- gpio-controller:
> - Usage: required
> - Value type: <none>
> - Definition: identifies this node as a gpio controller
> -
> -- #gpio-cells:
> - Usage: required
> - Value type: <u32>
> - Definition: must be 2. Specifying the pin number and flags, as defined
> - in <dt-bindings/gpio/gpio.h>
> -
> -- gpio-ranges:
> - Usage: required
> - Definition: see ../gpio/gpio.txt
> -
> -- gpio-reserved-ranges:
> - Usage: optional
> - Definition: see ../gpio/gpio.txt
> -
> -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
> -a general description of GPIO and interrupt bindings.
> -
> -Please refer to pinctrl-bindings.txt in this directory for details of the
> -common pinctrl bindings used by client devices, including the meaning of the
> -phrase "pin configuration node".
> -
> -The pin configuration nodes act as a container for an arbitrary number of
> -subnodes. Each of these subnodes represents some desired configuration for a
> -pin, a group, or a list of pins or groups. This configuration can include the
> -mux function to select on those pin(s)/group(s), and various pin configuration
> -parameters, such as pull-up, drive strength, etc.
> -
> -
> -PIN CONFIGURATION NODES:
> -
> -The name of each subnode is not important; all subnodes should be enumerated
> -and processed purely based on their content.
> -
> -Each subnode only affects those parameters that are explicitly listed. In
> -other words, a subnode that lists a mux function but no pin configuration
> -parameters implies no information about any pin configuration parameters.
> -Similarly, a pin subnode that describes a pullup parameter implies no
> -information about e.g. the mux function.
> -
> -
> -The following generic properties as defined in pinctrl-bindings.txt are valid
> -to specify in a pin configuration subnode:
> -
> -- pins:
> - Usage: required
> - Value type: <string-array>
> - Definition: List of gpio pins affected by the properties specified in
> - this subnode. Valid pins are:
> - gpio0-gpio69
> -
> -- function:
> - Usage: required
> - Value type: <string>
> - Definition: Specify the alternative function to be configured for the
> - specified pins. Functions are only valid for gpio pins.
> - Valid values are:
> - atest_char, atest_char0, atest_char1, atest_char2,
> - atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync,
> - audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync,
> - audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c,
> - blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart,
> - blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2,
> - blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0,
> - blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi,
> - blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1,
> - cxc0, cxc1, dbg_out, gcc_plltest, gcc_tlmm, gpio, ldo_en,
> - ldo_update, led0, led1, led2, mac0_sa0, mac0_sa1, mac1_sa0,
> - mac1_sa1, mac1_sa2, mac1_sa3, mac2_sa0, mac2_sa1, mdc,
> - mdio, pcie0_clk, pcie0_rst, pcie0_wake, pcie1_clk,
> - pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx, pcm_fsync,
> - pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0, pta1_1,
> - pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3,
> - qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
> - qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
> - qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
> - qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
> - qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
> - qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b,
> - qpic, rx0, rx1, rx2, sd_card, sd_write, tsens_max, wci2a,
> - wci2b, wci2c, wci2d
> -
> -- bias-disable:
> - Usage: optional
> - Value type: <none>
> - Definition: The specified pins should be configured as no pull.
> -
> -- bias-pull-down:
> - Usage: optional
> - Value type: <none>
> - Definition: The specified pins should be configured as pull down.
> -
> -- bias-pull-up:
> - Usage: optional
> - Value type: <none>
> - Definition: The specified pins should be configured as pull up.
> -
> -- output-high:
> - Usage: optional
> - Value type: <none>
> - Definition: The specified pins are configured in output mode, driven
> - high.
> -
> -- output-low:
> - Usage: optional
> - Value type: <none>
> - Definition: The specified pins are configured in output mode, driven
> - low.
> -
> -- drive-strength:
> - Usage: optional
> - Value type: <u32>
> - Definition: Selects the drive strength for the specified pins, in mA.
> - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
> -
> -Example:
> -
> - tlmm: pinctrl@1000000 {
> - compatible = "qcom,ipq8074-pinctrl";
> - reg = <0x1000000 0x300000>;
> - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - gpio-ranges = <&tlmm 0 0 70>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> -
> - uart2: uart2-default {
> - mux {
> - pins = "gpio23", "gpio24";
> - function = "blsp4_uart1";
> - };
> -
> - rx {
> - pins = "gpio23";
> - drive-strength = <4>;
> - bias-disable;
> - };
> -
> - tx {
> - pins = "gpio24";
> - drive-strength = <2>;
> - bias-pull-up;
> - };
> - };
> - };
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml
> new file mode 100644
> index 000000000000..c02dd2ad9b31
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml
> @@ -0,0 +1,135 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8074-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm IPQ8074 TLMM pin controller
> +
> +maintainers:
> + - Bjorn Andersson <[email protected]>
> + - Krzysztof Kozlowski <[email protected]>
> +
> +description:
> + Top Level Mode Multiplexer pin controller in Qualcomm IPQ8074 SoC.
> +
> +properties:
> + compatible:
> + const: qcom,ipq8074-pinctrl
> +
> + reg:
> + maxItems: 1
> +
> + interrupts: true
> + interrupt-controller: true
> + "#interrupt-cells": true
> + gpio-controller: true
> + "#gpio-cells": true
> + gpio-ranges: true
> + wakeup-parent: true
> +
> + gpio-reserved-ranges:
> + minItems: 1
> + maxItems: 35
> +
> + gpio-line-names:
> + maxItems: 70
> +
> +patternProperties:
> + "-state$":
> + oneOf:
> + - $ref: "#/$defs/qcom-ipq8074-tlmm-state"
> + - patternProperties:
> + "-pins$":
> + $ref: "#/$defs/qcom-ipq8074-tlmm-state"
> + additionalProperties: false
> +
> +$defs:
> + qcom-ipq8074-tlmm-state:
> + type: object
> + description:
> + Pinctrl node's client devices use subnodes for desired pin configuration.
> + Client device subnodes use below standard properties.
> + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
> +
> + properties:
> + pins:
> + description:
> + List of gpio pins affected by the properties specified in this
> + subnode.
> + items:
> + pattern: "^gpio([0-9]|[1-6][0-9]|70)$"
> + minItems: 1
> + maxItems: 36
> +
> + function:
> + description:
> + Specify the alternative function to be configured for the specified
> + pins.
> +
> + enum: [ gpio, atest_char, atest_char0, atest_char1, atest_char2,
> + atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync,
> + audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync,
> + audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c,
> + blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart,
> + blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2,
> + blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0,
> + blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi,
> + blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1, cxc0,
> + cxc1, dbg_out, gcc_plltest, gcc_tlmm, ldo_en, ldo_update, led0,
> + led1, led2, mac0_sa0, mac0_sa1, mac1_sa0, mac1_sa1, mac1_sa2,
> + mac1_sa3, mac2_sa0, mac2_sa1, mdc, mdio, pcie0_clk, pcie0_rst,
> + pcie0_wake, pcie1_clk, pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx,
> + pcm_fsync, pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0,
> + pta1_1, pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3,
> + qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
> + qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
> + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
> + qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,
> + qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
> + qdss_tracedata_b, qpic, rx0, rx1, rx2, sd_card, sd_write,
> + tsens_max, wci2a, wci2b, wci2c, wci2d ]
> +
> + bias-pull-down: true
> + bias-pull-up: true
> + bias-disable: true
> + drive-strength: true
> + input-enable: true
> + output-high: true
> + output-low: true
> +
> + required:
> + - pins
> +
> + additionalProperties: false
> +
> +allOf:
> + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + tlmm: pinctrl@1000000 {
> + compatible = "qcom,ipq8074-pinctrl";
> + reg = <0x01000000 0x300000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + gpio-ranges = <&tlmm 0 0 70>;
> + #gpio-cells = <0x2>;
> + interrupt-controller;
> + #interrupt-cells = <0x2>;
> +
> + serial4-state {
> + pins = "gpio23", "gpio24";
> + function = "blsp4_uart1";
> + drive-strength = <8>;
> + bias-disable;
> + };
> + };
> --
> 2.34.1
>
On Tue, 8 Nov 2022 15:23:56 +0100, Krzysztof Kozlowski wrote:
> Convert Qualcomm IPQ8074 pin controller bindings to DT schema. Keep the
> parsing of pin configuration subnodes consistent with other Qualcomm
> schemas (children named with '-state' suffix, their children with
> '-pins').
>
>
Applied, thanks!
[2/2] arm64: dts: qcom: ipq8074: align TLMM pin configuration with DT schema
commit: 1c3c31a6e7f6b467c160a4c58e385b2991e49139
Best regards,
--
Bjorn Andersson <[email protected]>
On Tue, 8 Nov 2022 15:23:56 +0100, Krzysztof Kozlowski wrote:
> Convert Qualcomm IPQ8074 pin controller bindings to DT schema. Keep the
> parsing of pin configuration subnodes consistent with other Qualcomm
> schemas (children named with '-state' suffix, their children with
> '-pins').
>
>
Applied, thanks!
[1/2] dt-bindings: pinctrl: qcom,ipq8074: convert to dtschema
Best regards,
--
Krzysztof Kozlowski <[email protected]>