2022-11-17 12:40:42

by Tomi Valkeinen

Subject: [PATCH v1 3/8] clk: renesas: r8a779g0: Add display related clocks

From: Tomi Valkeinen <[email protected]>

Add clocks related to display which are needed to get the DSI output
working.

Extracted from Renesas BSP tree.

Signed-off-by: Tomi Valkeinen <[email protected]>
---
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index c6337a408e5e..6937f1aee677 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -145,6 +145,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
+ DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
+ DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),

DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870),
DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870),
@@ -161,6 +163,14 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
+
+ DEF_MOD("dis0", 411, R8A779G0_CLK_S0D3),
+ DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_DSIREF),
+ DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_DSIREF),
+
+ DEF_MOD("fcpvd0", 508, R8A779G0_CLK_S0D3),
+ DEF_MOD("fcpvd1", 509, R8A779G0_CLK_S0D3),
+
DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1),
DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1),
DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1),
@@ -193,6 +203,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
+
+ DEF_MOD("vspd0", 830, R8A779G0_CLK_S0D1_VIO),
+ DEF_MOD("vspd1", 831, R8A779G0_CLK_S0D1_VIO),
+
DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
DEF_MOD("cmt0", 910, R8A779G0_CLK_R),
DEF_MOD("cmt1", 911, R8A779G0_CLK_R),
--
2.34.1

2022-11-17 14:29:33

by Kieran Bingham

Subject: Re: [PATCH v1 3/8] clk: renesas: r8a779g0: Add display related clocks

Quoting Tomi Valkeinen (2022-11-17 12:25:42)
> From: Tomi Valkeinen <[email protected]>
>
> Add clocks related to display which are needed to get the DSI output
> working.
>
> Extracted from Renesas BSP tree.
>
> Signed-off-by: Tomi Valkeinen <[email protected]>
> ---
> drivers/clk/renesas/r8a779g0-cpg-mssr.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> index c6337a408e5e..6937f1aee677 100644
> --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> @@ -145,6 +145,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
> DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
> DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
> DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
> + DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
> + DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
>
> DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870),
> DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870),
> @@ -161,6 +163,14 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
> DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
> DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
> DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
> +
> + DEF_MOD("dis0", 411, R8A779G0_CLK_S0D3),

dsi0?

Oh - how curious - it's listed as dis0 in the datasheet.
Ok - so this is the DU *display* not DSI ;-)

> + DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_DSIREF),
> + DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_DSIREF),
> +
> + DEF_MOD("fcpvd0", 508, R8A779G0_CLK_S0D3),
> + DEF_MOD("fcpvd1", 509, R8A779G0_CLK_S0D3),
> +

checks out. I guess the fcpcs is the CSI related FCP ? Anyway, if it's
not needed it can be ignored for now.


> DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1),
> DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1),
> DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1),
> @@ -193,6 +203,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
> DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2),
> DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2),
> DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
> +
> + DEF_MOD("vspd0", 830, R8A779G0_CLK_S0D1_VIO),
> + DEF_MOD("vspd1", 831, R8A779G0_CLK_S0D1_VIO),
> +

Reviewed-by: Kieran Bingham <[email protected]>

> DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
> DEF_MOD("cmt0", 910, R8A779G0_CLK_R),
> DEF_MOD("cmt1", 911, R8A779G0_CLK_R),
> --
> 2.34.1
>

2022-11-22 03:05:17

by Laurent Pinchart

Subject: Re: [PATCH v1 3/8] clk: renesas: r8a779g0: Add display related clocks

On Thu, Nov 17, 2022 at 02:08:57PM +0000, Kieran Bingham wrote:
> Quoting Tomi Valkeinen (2022-11-17 12:25:42)
> > From: Tomi Valkeinen <[email protected]>
> >
> > Add clocks related to display which are needed to get the DSI output
> > working.
> >
> > Extracted from Renesas BSP tree.
> >
> > Signed-off-by: Tomi Valkeinen <[email protected]>
> > ---
> > drivers/clk/renesas/r8a779g0-cpg-mssr.c | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> > index c6337a408e5e..6937f1aee677 100644
> > --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> > @@ -145,6 +145,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
> > DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
> > DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
> > DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
> > + DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
> > + DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
> >
> > DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870),
> > DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870),
> > @@ -161,6 +163,14 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
> > DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
> > DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
> > DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
> > +
> > + DEF_MOD("dis0", 411, R8A779G0_CLK_S0D3),
>
> dsi0?
>
> Oh - how curious - it's listed as dis0 in the datasheet.
> Ok - so this is the DU *display* not DSI ;-)
>
> > + DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_DSIREF),
> > + DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_DSIREF),
> > +
> > + DEF_MOD("fcpvd0", 508, R8A779G0_CLK_S0D3),
> > + DEF_MOD("fcpvd1", 509, R8A779G0_CLK_S0D3),
> > +
>
> checks out. I guess the fcpcs is the CSI related FCP ? Anyway, if it's
> not needed it can be ignored for now.
>
>
> > DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1),
> > DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1),
> > DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1),
> > @@ -193,6 +203,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
> > DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2),
> > DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2),
> > DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
> > +
> > + DEF_MOD("vspd0", 830, R8A779G0_CLK_S0D1_VIO),
> > + DEF_MOD("vspd1", 831, R8A779G0_CLK_S0D1_VIO),
> > +
>
> Reviewed-by: Kieran Bingham <[email protected]>

I can't verify the MSTP clock parents, I assume they come from the BSP,
so

Reviewed-by: Laurent Pinchart <[email protected]>

> > DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
> > DEF_MOD("cmt0", 910, R8A779G0_CLK_R),
> > DEF_MOD("cmt1", 911, R8A779G0_CLK_R),

--
Regards,

Laurent Pinchart