2022-11-17 12:41:02

by Tomi Valkeinen

Subject: [PATCH v1 4/8] arm64: dts: renesas: r8a779g0: Add display related data

From: Tomi Valkeinen <[email protected]>

Add DT nodes for components needed to get the DSI output working:
- FCPv
- VSPd
- DU
- DSI

Signed-off-by: Tomi Valkeinen <[email protected]>
---
arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 129 ++++++++++++++++++++++
1 file changed, 129 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 45d8d927ad26..31d4930c5adc 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -1207,6 +1207,135 @@ prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
+
+ fcpvd0: fcp@fea10000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea10000 0 0x200>;
+ clocks = <&cpg CPG_MOD 508>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 508>;
+ };
+
+ fcpvd1: fcp@fea11000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea11000 0 0x200>;
+ clocks = <&cpg CPG_MOD 509>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 509>;
+ };
+
+ vspd0: vsp@fea20000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea20000 0 0x5000>;
+ interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 830>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 830>;
+
+ renesas,fcp = <&fcpvd0>;
+ };
+
+ vspd1: vsp@fea28000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea28000 0 0x5000>;
+ interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 831>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 831>;
+
+ renesas,fcp = <&fcpvd1>;
+ };
+
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a779g0";
+ reg = <0 0xfeb00000 0 0x40000>;
+ interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 411>;
+ clock-names = "du.0";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 411>;
+ reset-names = "du.0";
+ renesas,vsps = <&vspd0 0>, <&vspd1 0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_dsi0: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ du_out_dsi1: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi-encoder@fed80000 {
+ compatible = "renesas,r8a779g0-dsi-csi2-tx";
+ reg = <0 0xfed80000 0 0x10000>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ clocks = <&cpg CPG_MOD 415>,
+ <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
+ <&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
+ clock-names = "fck", "dsi", "pll";
+ resets = <&cpg 415>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&du_out_dsi0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ dsi1: dsi-encoder@fed90000 {
+ compatible = "renesas,r8a779g0-dsi-csi2-tx";
+ reg = <0 0xfed90000 0 0x10000>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ clocks = <&cpg CPG_MOD 416>,
+ <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
+ <&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
+ clock-names = "fck", "dsi", "pll";
+ resets = <&cpg 416>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi1_in: endpoint {
+ remote-endpoint = <&du_out_dsi1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
};

timer {
--
2.34.1

2022-11-17 15:23:34

by Kieran Bingham

Subject: Re: [PATCH v1 4/8] arm64: dts: renesas: r8a779g0: Add display related data

Quoting Tomi Valkeinen (2022-11-17 12:25:43)
> From: Tomi Valkeinen <[email protected]>
>
> Add DT nodes for components needed to get the DSI output working:
> - FCPv
> - VSPd
> - DU
> - DSI
>
> Signed-off-by: Tomi Valkeinen <[email protected]>
> ---
> arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 129 ++++++++++++++++++++++
> 1 file changed, 129 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> index 45d8d927ad26..31d4930c5adc 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> @@ -1207,6 +1207,135 @@ prr: chipid@fff00044 {
> compatible = "renesas,prr";
> reg = <0 0xfff00044 0 4>;
> };

I think these nodes are supposed to be in sort order based on the
register address in memory.

Disregarding sort order, I'll review the node contents.

I would probably s/data/nodes/ in $SUBJECT too.


> +
> + fcpvd0: fcp@fea10000 {
> + compatible = "renesas,fcpv";
> + reg = <0 0xfea10000 0 0x200>;
> + clocks = <&cpg CPG_MOD 508>;
> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> + resets = <&cpg 508>;
> + };
> +
> + fcpvd1: fcp@fea11000 {
> + compatible = "renesas,fcpv";
> + reg = <0 0xfea11000 0 0x200>;
> + clocks = <&cpg CPG_MOD 509>;
> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> + resets = <&cpg 509>;
> + };

I'm intrigued at the length of 0x200 as I only see 3 registers up to
0x0018 ..

But all existing platforms with fcpv* set 0x200 ... so lets cargo cult it up... :-)

> +
> + vspd0: vsp@fea20000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xfea20000 0 0x5000>;

"""
Below are the base addresses of each VSP unit. VSPX has 32Kbyte address
space. VSPD has 28Kbyte address space.
"""

Hrm : 28K is 0x7000

RPf n OSD CLUT Table: H’4000 + H’0400*n to H’43fc + H’0400*n

0x43fc+(0x400*5)
22524 [0x57fc]

So this needs to be /at least/ 0x6000 (Would 0x5800 be odd?) and perhaps as it clearly states
28k, we should just set it to 0x7000.



> + interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 830>;
> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> + resets = <&cpg 830>;
> +
> + renesas,fcp = <&fcpvd0>;
> + };
> +
> + vspd1: vsp@fea28000 {
> + compatible = "renesas,vsp2";
> + reg = <0 0xfea28000 0 0x5000>;

Same here of course (reg = <0 0xfea28000 0 0x7000>)


> + interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 831>;
> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> + resets = <&cpg 831>;
> +
> + renesas,fcp = <&fcpvd1>;
> + };
> +
> + du: display@feb00000 {
> + compatible = "renesas,du-r8a779g0";
> + reg = <0 0xfeb00000 0 0x40000>;
> + interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 411>;
> + clock-names = "du.0";
> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> + resets = <&cpg 411>;
> + reset-names = "du.0";
> + renesas,vsps = <&vspd0 0>, <&vspd1 0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + du_out_dsi0: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + du_out_dsi1: endpoint {
> + remote-endpoint = <&dsi1_in>;
> + };
> + };
> + };
> + };
> +
> + dsi0: dsi-encoder@fed80000 {
> + compatible = "renesas,r8a779g0-dsi-csi2-tx";
> + reg = <0 0xfed80000 0 0x10000>;
> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> + clocks = <&cpg CPG_MOD 415>,
> + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
> + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
> + clock-names = "fck", "dsi", "pll";
> + resets = <&cpg 415>;

blank line here to separate it, and highlight that it's disabled? (Like
is done for DU?

> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&du_out_dsi0>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> + dsi1: dsi-encoder@fed90000 {
> + compatible = "renesas,r8a779g0-dsi-csi2-tx";
> + reg = <0 0xfed90000 0 0x10000>;
> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> + clocks = <&cpg CPG_MOD 416>,
> + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
> + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
> + clock-names = "fck", "dsi", "pll";
> + resets = <&cpg 416>;

Same.

With the VSPD register ranges increased accordingly:

Reviewed-by: Kieran Bingham <[email protected]>

> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi1_in: endpoint {
> + remote-endpoint = <&du_out_dsi1>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> };
>
> timer {
> --
> 2.34.1
>

2022-11-22 03:16:51

by Laurent Pinchart

Subject: Re: [PATCH v1 4/8] arm64: dts: renesas: r8a779g0: Add display related data

On Thu, Nov 17, 2022 at 03:03:39PM +0000, Kieran Bingham wrote:
> Quoting Tomi Valkeinen (2022-11-17 12:25:43)
> > From: Tomi Valkeinen <[email protected]>
> >
> > Add DT nodes for components needed to get the DSI output working:
> > - FCPv
> > - VSPd
> > - DU
> > - DSI
> >
> > Signed-off-by: Tomi Valkeinen <[email protected]>
> > ---
> > arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 129 ++++++++++++++++++++++
> > 1 file changed, 129 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> > index 45d8d927ad26..31d4930c5adc 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> > @@ -1207,6 +1207,135 @@ prr: chipid@fff00044 {
> > compatible = "renesas,prr";
> > reg = <0 0xfff00044 0 4>;
> > };
>
> I think these nodes are supposed to be in sort order based on the
> register address in memory.
>
> Disregarding sort order, I'll review the node contents.
>
> I would probably s/data/nodes/ in $SUBJECT too.
>
> > +
> > + fcpvd0: fcp@fea10000 {
> > + compatible = "renesas,fcpv";
> > + reg = <0 0xfea10000 0 0x200>;
> > + clocks = <&cpg CPG_MOD 508>;
> > + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> > + resets = <&cpg 508>;
> > + };
> > +
> > + fcpvd1: fcp@fea11000 {
> > + compatible = "renesas,fcpv";
> > + reg = <0 0xfea11000 0 0x200>;
> > + clocks = <&cpg CPG_MOD 509>;
> > + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> > + resets = <&cpg 509>;
> > + };
>
> I'm intrigued at the length of 0x200 as I only see 3 registers up to
> 0x0018 ..
>
> But all existing platforms with fcpv* set 0x200 ... so lets cargo cult it up... :-)
>
> > +
> > + vspd0: vsp@fea20000 {
> > + compatible = "renesas,vsp2";
> > + reg = <0 0xfea20000 0 0x5000>;
>
> """
> Below are the base addresses of each VSP unit. VSPX has 32Kbyte address
> space. VSPD has 28Kbyte address space.
> """
>
> Hrm : 28K is 0x7000
>
> RPf n OSD CLUT Table: H’4000 + H’0400*n to H’43fc + H’0400*n
>
> 0x43fc+(0x400*5)
> 22524 [0x57fc]
>
> So this needs to be /at least/ 0x6000 (Would 0x5800 be odd?) and perhaps as it clearly states
> 28k, we should just set it to 0x7000.

I'd go for 0x7000 indeed.

> > + interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 830>;
> > + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> > + resets = <&cpg 830>;
> > +
> > + renesas,fcp = <&fcpvd0>;
> > + };
> > +
> > + vspd1: vsp@fea28000 {
> > + compatible = "renesas,vsp2";
> > + reg = <0 0xfea28000 0 0x5000>;
>
> Same here of course (reg = <0 0xfea28000 0 0x7000>)
>
> > + interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 831>;
> > + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> > + resets = <&cpg 831>;
> > +
> > + renesas,fcp = <&fcpvd1>;
> > + };
> > +
> > + du: display@feb00000 {
> > + compatible = "renesas,du-r8a779g0";
> > + reg = <0 0xfeb00000 0 0x40000>;
> > + interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 411>;
> > + clock-names = "du.0";
> > + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> > + resets = <&cpg 411>;
> > + reset-names = "du.0";
> > + renesas,vsps = <&vspd0 0>, <&vspd1 0>;
> > +
> > + status = "disabled";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + du_out_dsi0: endpoint {
> > + remote-endpoint = <&dsi0_in>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + du_out_dsi1: endpoint {
> > + remote-endpoint = <&dsi1_in>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + dsi0: dsi-encoder@fed80000 {
> > + compatible = "renesas,r8a779g0-dsi-csi2-tx";
> > + reg = <0 0xfed80000 0 0x10000>;
> > + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> > + clocks = <&cpg CPG_MOD 415>,
> > + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
> > + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
> > + clock-names = "fck", "dsi", "pll";
> > + resets = <&cpg 415>;
>
> blank line here to separate it, and highlight that it's disabled? (Like
> is done for DU?
>
> > + status = "disabled";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + dsi0_in: endpoint {
> > + remote-endpoint = <&du_out_dsi0>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + };
> > + };
> > + };
> > +
> > + dsi1: dsi-encoder@fed90000 {
> > + compatible = "renesas,r8a779g0-dsi-csi2-tx";
> > + reg = <0 0xfed90000 0 0x10000>;
> > + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> > + clocks = <&cpg CPG_MOD 416>,
> > + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
> > + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
> > + clock-names = "fck", "dsi", "pll";
> > + resets = <&cpg 416>;
>
> Same.
>
> With the VSPD register ranges increased accordingly:
>
> Reviewed-by: Kieran Bingham <[email protected]>
>
> > + status = "disabled";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + dsi1_in: endpoint {
> > + remote-endpoint = <&du_out_dsi1>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + };
> > + };
> > + };
> > +

Extra blank line.

Reviewed-by: Laurent Pinchart <[email protected]>

> > };
> >
> > timer {

--
Regards,

Laurent Pinchart

2022-11-22 10:15:28

by Tomi Valkeinen

Subject: Re: [PATCH v1 4/8] arm64: dts: renesas: r8a779g0: Add display related data

On 17/11/2022 17:03, Kieran Bingham wrote:
> Quoting Tomi Valkeinen (2022-11-17 12:25:43)
>> From: Tomi Valkeinen <[email protected]>
>>
>> Add DT nodes for components needed to get the DSI output working:
>> - FCPv
>> - VSPd
>> - DU
>> - DSI
>>
>> Signed-off-by: Tomi Valkeinen <[email protected]>
>> ---
>> arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 129 ++++++++++++++++++++++
>> 1 file changed, 129 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
>> index 45d8d927ad26..31d4930c5adc 100644
>> --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
>> @@ -1207,6 +1207,135 @@ prr: chipid@fff00044 {
>> compatible = "renesas,prr";
>> reg = <0 0xfff00044 0 4>;
>> };
>
> I think these nodes are supposed to be in sort order based on the
> register address in memory.

Ah, I didn't realize that.

> Disregarding sort order, I'll review the node contents.
>
> I would probably s/data/nodes/ in $SUBJECT too.
>
>
>> +
>> + fcpvd0: fcp@fea10000 {
>> + compatible = "renesas,fcpv";
>> + reg = <0 0xfea10000 0 0x200>;
>> + clocks = <&cpg CPG_MOD 508>;
>> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
>> + resets = <&cpg 508>;
>> + };
>> +
>> + fcpvd1: fcp@fea11000 {
>> + compatible = "renesas,fcpv";
>> + reg = <0 0xfea11000 0 0x200>;
>> + clocks = <&cpg CPG_MOD 509>;
>> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
>> + resets = <&cpg 509>;
>> + };
>
> I'm intrigued at the length of 0x200 as I only see 3 registers up to
> 0x0018 ..
>
> But all existing platforms with fcpv* set 0x200 ... so lets cargo cult it up... :-)
>
>> +
>> + vspd0: vsp@fea20000 {
>> + compatible = "renesas,vsp2";
>> + reg = <0 0xfea20000 0 0x5000>;
>
> """
> Below are the base addresses of each VSP unit. VSPX has 32Kbyte address
> space. VSPD has 28Kbyte address space.
> """
>
> Hrm : 28K is 0x7000
>
> RPf n OSD CLUT Table: H’4000 + H’0400*n to H’43fc + H’0400*n
>
> 0x43fc+(0x400*5)
> 22524 [0x57fc]
>
> So this needs to be /at least/ 0x6000 (Would 0x5800 be odd?) and perhaps as it clearly states
> 28k, we should just set it to 0x7000.

Ok. These are identical to v3u, and I was just copying v3u's dts,
assuming they're correct. We probably should fix the v3u dts files too.

>
>> + interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 830>;
>> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
>> + resets = <&cpg 830>;
>> +
>> + renesas,fcp = <&fcpvd0>;
>> + };
>> +
>> + vspd1: vsp@fea28000 {
>> + compatible = "renesas,vsp2";
>> + reg = <0 0xfea28000 0 0x5000>;
>
> Same here of course (reg = <0 0xfea28000 0 0x7000>)
>
>
>> + interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 831>;
>> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
>> + resets = <&cpg 831>;
>> +
>> + renesas,fcp = <&fcpvd1>;
>> + };
>> +
>> + du: display@feb00000 {
>> + compatible = "renesas,du-r8a779g0";
>> + reg = <0 0xfeb00000 0 0x40000>;
>> + interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 411>;
>> + clock-names = "du.0";
>> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
>> + resets = <&cpg 411>;
>> + reset-names = "du.0";
>> + renesas,vsps = <&vspd0 0>, <&vspd1 0>;
>> +
>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + du_out_dsi0: endpoint {
>> + remote-endpoint = <&dsi0_in>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + du_out_dsi1: endpoint {
>> + remote-endpoint = <&dsi1_in>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + dsi0: dsi-encoder@fed80000 {
>> + compatible = "renesas,r8a779g0-dsi-csi2-tx";
>> + reg = <0 0xfed80000 0 0x10000>;
>> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
>> + clocks = <&cpg CPG_MOD 415>,
>> + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
>> + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
>> + clock-names = "fck", "dsi", "pll";
>> + resets = <&cpg 415>;
>
> blank line here to separate it, and highlight that it's disabled? (Like
> is done for DU?

Ok.

>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + dsi0_in: endpoint {
>> + remote-endpoint = <&du_out_dsi0>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + };
>> + };
>> + };
>> +
>> + dsi1: dsi-encoder@fed90000 {
>> + compatible = "renesas,r8a779g0-dsi-csi2-tx";
>> + reg = <0 0xfed90000 0 0x10000>;
>> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
>> + clocks = <&cpg CPG_MOD 416>,
>> + <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
>> + <&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
>> + clock-names = "fck", "dsi", "pll";
>> + resets = <&cpg 416>;
>
> Same.
>
> With the VSPD register ranges increased accordingly:
>
> Reviewed-by: Kieran Bingham <[email protected]>
>
>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + dsi1_in: endpoint {
>> + remote-endpoint = <&du_out_dsi1>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + };
>> + };
>> + };
>> +
>> };
>>
>> timer {
>> --
>> 2.34.1
>>