DCC(Data Capture and Compare) is a DMA engine designed for debugging purposes.
In case of a system crash or manual software triggers by the user the DCC hardware
stores the value at the register addresses which can be used for debugging purposes.
The DCC driver provides the user with debugfs interface to configure the register
addresses. The options that the DCC hardware provides include reading from registers,
writing to registers, first reading and then writing to registers and looping
through the values of the same register.
In certain cases a register write needs to be executed for accessing the rest of the
registers, also the user might want to record the changing values of a register with
time for which he has the option to use the loop feature.
The options mentioned above are exposed to the user by debugfs files once the driver
is probed. The details and usage of this debugfs files are documented in
Documentation/ABI/testing/debugfs-driver-dcc.
As an example let us consider a couple of debug scenarios where DCC has been proved to be
effective for debugging purposes:-
i)TimeStamp Related Issue
On SC7180, there was a coresight timestamp issue where it would occasionally be all 0
instead of proper timestamp values.
Proper timestamp:
Idx:3373; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x13004d8f5b7aa; CC=0x9e
Zero timestamp:
Idx:3387; ID:10; I_TIMESTAMP : Timestamp.; Updated val = 0x0; CC=0xa2
Now this is a non-fatal issue and doesn't need a system reset, but still needs
to be rootcaused and fixed for those who do care about coresight etm traces.
Since this is a timestamp issue, we would be looking for any timestamp related
clocks and such.
We get all the clk register details from IP documentation and configure it
via DCC config_read debugfs node. Before that we set the current linked list.
/* Program the linked list with the addresses */
echo R 0x10c004 > /sys/kernel/debug/dcc/../3/config
echo R 0x10c008 > /sys/kernel/debug/dcc/../3/config
echo R 0x10c00c > /sys/kernel/debug/dcc/../3/config
echo R 0x10c010 > /sys/kernel/debug/dcc/../3/config
..... and so on for other timestamp related clk registers
/* Other way of specifying is in "addr len" pair, in below case it
specifies to capture 4 words starting 0x10C004 */
echo R 0x10C004 4 > /sys/kernel/debug/dcc/../3/config_read
/* Enable DCC */
echo 1 > /sys/kernel/debug/dcc/../3/enable
/* Run the timestamp test for working case */
/* Send SW trigger */
echo 1 > /sys/kernel/debug/dcc/../trigger
/* Read SRAM */
cat /dev/dcc_sram > dcc_sram1.bin
/* Run the timestamp test for non-working case */
/* Send SW trigger */
echo 1 > /sys/kernel/debug/dcc/../trigger
/* Read SRAM */
cat /dev/dcc_sram > dcc_sram2.bin
Get the parser from [1] and checkout the latest branch.
/* Parse the SRAM bin */
python dcc_parser.py -s dcc_sram1.bin --v2 -o output/
python dcc_parser.py -s dcc_sram2.bin --v2 -o output/
Sample parsed output of dcc_sram1.bin:
<hwioDump version="1">
<timestamp>03/14/21</timestamp>
<generator>Linux DCC Parser</generator>
<chip name="None" version="None">
<register address="0x0010c004" value="0x80000000" />
<register address="0x0010c008" value="0x00000008" />
<register address="0x0010c00c" value="0x80004220" />
<register address="0x0010c010" value="0x80000000" />
</chip>
<next_ll_offset>next_ll_offset : 0x1c </next_ll_offset>
</hwioDump>
ii)NOC register errors
A particular class of registers called NOC which are functional registers was reporting
errors while logging the values.To trace these errors the DCC has been used effectively.
The steps followed were similar to the ones mentioned above.
In addition to NOC registers a few other dependent registers were configured in DCC to
monitor it's values during a crash. A look at the dependent register values revealed that
the crash was happening due to a secured access to one of these dependent registers.
All these debugging activity and finding the root cause was achieved using DCC.
DCC parser is available at the following open source location
https://source.codeaurora.org/quic/la/platform/vendor/qcom-opensource/tools/tree/dcc_parser
Changes in V21
*Implemented the comments on V20 of the patch.
Souradeep Chowdhury (7):
dt-bindings: soc: qcom,dcc: Add the dtschema
soc: qcom: dcc: Add driver support for Data Capture and Compare
unit(DCC)
MAINTAINERS: Add the entry for DCC(Data Capture and Compare) driver
support
arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support
node
arm64: dts: qcom: sc7280: Add Data Capture and Compare(DCC) support
node
arm64: dts: qcom: sc7180: Add Data Capture and Compare(DCC) support
node
arm64: dts: qcom: sdm845: Add Data Capture and Compare(DCC) support
node
Documentation/ABI/testing/debugfs-driver-dcc | 98 ++
.../devicetree/bindings/soc/qcom/qcom,dcc.yaml | 44 +
MAINTAINERS | 8 +
arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 +
arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +
arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 +
arch/arm64/boot/dts/qcom/sm8150.dtsi | 6 +
drivers/soc/qcom/Kconfig | 8 +
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/dcc.c | 1305 ++++++++++++++++++++
10 files changed, 1488 insertions(+)
create mode 100644 Documentation/ABI/testing/debugfs-driver-dcc
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,dcc.yaml
create mode 100644 drivers/soc/qcom/dcc.c
--
2.7.4
Add the device tree bindings for Data Capture and Compare(DCC).
Signed-off-by: Souradeep Chowdhury <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/soc/qcom/qcom,dcc.yaml | 44 ++++++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,dcc.yaml
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,dcc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,dcc.yaml
new file mode 100644
index 0000000..ce7e20d
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,dcc.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,dcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Data Capture and Compare
+
+maintainers:
+ - Souradeep Chowdhury <[email protected]>
+
+description: |
+ DCC (Data Capture and Compare) is a DMA engine which is used to save
+ configuration data or system memory contents during catastrophic failure
+ or SW trigger. DCC is used to capture and store data for debugging purpose
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,sm8150-dcc
+ - qcom,sc7280-dcc
+ - qcom,sc7180-dcc
+ - qcom,sdm845-dcc
+ - const: qcom,dcc
+
+ reg:
+ items:
+ - description: DCC base
+ - description: DCC RAM base
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ dma@10a2000{
+ compatible = "qcom,sm8150-dcc", "qcom,dcc";
+ reg = <0x010a2000 0x1000>,
+ <0x010ad000 0x2000>;
+ };
--
2.7.4
Add the DCC(Data Capture and Compare) device tree node entry along with
the address of the register region.
Signed-off-by: Souradeep Chowdhury <[email protected]>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index d761da4..7d476b2 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2137,6 +2137,12 @@
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
+ dma@10a2000 {
+ compatible = "qcom,sdm845-dcc", "qcom,dcc";
+ reg = <0x0 0x010a2000 0x0 0x1000>,
+ <0x0 0x010ae000 0x0 0x2000>;
+ };
+
pmu@114a000 {
compatible = "qcom,sdm845-llcc-bwmon";
reg = <0 0x0114a000 0 0x1000>;
--
2.7.4
Add the DCC(Data Capture and Compare) device tree node entry along with
the address of the register region.
Signed-off-by: Souradeep Chowdhury <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 58976a1..3b1bcad 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2089,6 +2089,12 @@
#power-domain-cells = <1>;
};
+ dma@10a2000 {
+ compatible = "qcom,sc7180-dcc", "qcom,dcc";
+ reg = <0x0 0x010a2000 0x0 0x1000>,
+ <0x0 0x010ae000 0x0 0x2000>;
+ };
+
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,
--
2.7.4
Add the entries for all the files added as a part of driver support for
DCC(Data Capture and Compare).
Signed-off-by: Souradeep Chowdhury <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index cddc0ae..0fa438b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5720,6 +5720,14 @@ F: include/linux/tfrc.h
F: include/uapi/linux/dccp.h
F: net/dccp/
+DCC QTI DRIVER
+M: Souradeep Chowdhury <[email protected]>
+L: [email protected]
+S: Maintained
+F: Documentation/ABI/testing/debugfs-driver-dcc
+F: Documentation/devicetree/bindings/soc/qcom/qcom,dcc.yaml
+F: drivers/soc/qcom/dcc.c
+
DECnet NETWORK LAYER
L: [email protected]
S: Orphan
--
2.7.4
Add the DCC(Data Capture and Compare) device tree node entry along with
the addresses for register regions.
Signed-off-by: Souradeep Chowdhury <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index cef8c4f..38a840b 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1767,6 +1767,12 @@
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
+ dma@10a2000 {
+ compatible = "qcom,sm8150-dcc", "qcom,dcc";
+ reg = <0x0 0x010a2000 0x0 0x1000>,
+ <0x0 0x010ad000 0x0 0x3000>;
+ };
+
pcie0: pci@1c00000 {
compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
reg = <0 0x01c00000 0 0x3000>,
--
2.7.4
On Tue, 27 Dec 2022 20:52:44 +0530, Souradeep Chowdhury wrote:
> DCC(Data Capture and Compare) is a DMA engine designed for debugging purposes.
> In case of a system crash or manual software triggers by the user the DCC hardware
> stores the value at the register addresses which can be used for debugging purposes.
> The DCC driver provides the user with debugfs interface to configure the register
> addresses. The options that the DCC hardware provides include reading from registers,
> writing to registers, first reading and then writing to registers and looping
> through the values of the same register.
>
> [...]
Applied, thanks!
[4/7] arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support node
commit: d4b94c8244919742417c3a165ef73081de37ef3b
[5/7] arm64: dts: qcom: sc7280: Add Data Capture and Compare(DCC) support node
commit: 029d6586dc2d1d10e9df3962633e29e145d764ec
[6/7] arm64: dts: qcom: sc7180: Add Data Capture and Compare(DCC) support node
commit: add74cad7c9d1bf59d41b229852f3ebe0be4a84f
[7/7] arm64: dts: qcom: sdm845: Add Data Capture and Compare(DCC) support node
commit: 91269c425649baad9758dbe269e7069ad7fa05fc
Best regards,
--
Bjorn Andersson <[email protected]>