Add resets and remove qdsp6ss clcok controller for audioreach based platforms.
Chnges since v1:
-- Update commit message.
-- Remove qdsp6ss clock control.
Srinivasa Rao Mandadapu (4):
dt-bindings: clock: qcom,sc7280-lpasscc: Remove qdsp6ss reg property
dt-bindings: clock: qcom,sc7280-lpasscc: Add resets for audioreach
clk: qcom: lpasscc-sc7280: Remove qdsp6ss clock control
clk: qcom: lpasscc-sc7280: Add resets for audioreach
.../bindings/clock/qcom,sc7280-lpasscc.yaml | 14 +++--
drivers/clk/qcom/lpasscc-sc7280.c | 66 +++++-----------------
2 files changed, 22 insertions(+), 58 deletions(-)
--
2.7.4
Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
for audioreach based SC7280 platforms.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Tested-by: Mohammad Rafi Shaik <[email protected]>
---
.../devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
index 9c72b8e..40fc6ab 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
@@ -31,13 +31,18 @@ properties:
'#clock-cells':
const: 1
+ '#reset-cells':
+ const: 1
+
reg:
items:
- description: LPASS top-cc register
+ - description: LPASS reset-cgcr register
reg-names:
items:
- const: top_cc
+ - const: reset_cgcr
required:
- compatible
@@ -54,10 +59,11 @@ examples:
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
clock-controller@3c04000 {
compatible = "qcom,sc7280-lpasscc";
- reg = <0x03c04000 0x4>;
- reg-names = "top_cc";
+ reg = <0x03c04000 0x4>, <0x032a9000 0x1000>;
+ reg-names = "top_cc", "reset_cgcr";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
+ #reset-cells = <1>;
};
...
--
2.7.4
The clock gating control for TX/RX/WSA core bus clocks would be required
to be reset(moved from hardware control) from audio core driver. Thus
add the support for the reset clocks in audioreach based clock driver.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Tested-by: Mohammad Rafi Shaik <[email protected]>
---
drivers/clk/qcom/lpasscc-sc7280.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c
index 87e1c21..a7f4ed4 100644
--- a/drivers/clk/qcom/lpasscc-sc7280.c
+++ b/drivers/clk/qcom/lpasscc-sc7280.c
@@ -12,10 +12,12 @@
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
+#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
#include "clk-regmap.h"
#include "clk-branch.h"
#include "common.h"
+#include "reset.h"
static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
.halt_reg = 0x0,
@@ -48,6 +50,18 @@ static const struct qcom_cc_desc lpass_cc_top_sc7280_desc = {
.num_clks = ARRAY_SIZE(lpass_cc_top_sc7280_clocks),
};
+static const struct qcom_reset_map lpass_cc_sc7280_resets[] = {
+ [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
+ [LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 },
+ [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
+};
+
+static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = {
+ .config = &lpass_regmap_config,
+ .resets = lpass_cc_sc7280_resets,
+ .num_resets = ARRAY_SIZE(lpass_cc_sc7280_resets),
+};
+
static int lpass_cc_sc7280_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *desc;
@@ -71,6 +85,13 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev)
if (ret)
goto destroy_pm_clk;
+ lpass_regmap_config.name = "reset_cgcr";
+ desc = &lpass_audio_cc_reset_sc7280_desc;
+
+ ret = qcom_cc_probe_by_index(pdev, 1, desc);
+ if (ret)
+ goto destroy_pm_clk;
+
return 0;
destroy_pm_clk:
--
2.7.4
On 30/12/2022 14:43, Srinivasa Rao Mandadapu wrote:
> Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
> for audioreach based SC7280 platforms.
>
> Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
> Tested-by: Mohammad Rafi Shaik <[email protected]>
> ---
> .../devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
> index 9c72b8e..40fc6ab 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
> @@ -31,13 +31,18 @@ properties:
> '#clock-cells':
> const: 1
>
> + '#reset-cells':
> + const: 1
> +
> reg:
> items:
> - description: LPASS top-cc register
> + - description: LPASS reset-cgcr register
It's now even a bigger mess. First ABI break, then bring it back to
previous stage - so two IO addresses - but with different values! There
is no way this works with other systems or DTS users.
>
> reg-names:
> items:
> - const: top_cc
> + - const: reset_cgcr
The 'reg-names' is only a helper, order and contents of 'reg' is fixed.
Best regards,
Krzysztof