Add resets and remove qdsp6ss clcok controller for audioreach based platforms.
Changes since v2:
-- Revert removing qdsp6ss clock control.
-- Add Conditional check for qdsp6ss clock registration.
Changes since v1:
-- Update commit message.
-- Remove qdsp6ss clock control.
Srinivasa Rao Mandadapu (4):
dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode
property
dt-bindings: clock: qcom,sc7280-lpasscc: Add resets for audioreach
clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration
clk: qcom: lpasscc-sc7280: Add resets for audioreach
.../bindings/clock/qcom,sc7280-lpasscc.yaml | 19 ++++++++++--
drivers/clk/qcom/lpasscc-sc7280.c | 35 ++++++++++++++++++----
2 files changed, 47 insertions(+), 7 deletions(-)
--
2.7.4
The qdsp6ss memory region is being shared by ADSP remoteproc device and
lpasscc clock device, hence causing memory conflict.
As the qdsp6ss clocks are being enabled in remoteproc driver, skip qdsp6ss
clock registration if "qcom,adsp-pil-mode" is enabled.
Fixes: 4ab43d171181 ("clk: qcom: Add lpass clock controller driver for SC7280")
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Tested-by: Mohammad Rafi Shaik <[email protected]>
---
drivers/clk/qcom/lpasscc-sc7280.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c
index 5c1e17b..e1af32c 100644
--- a/drivers/clk/qcom/lpasscc-sc7280.c
+++ b/drivers/clk/qcom/lpasscc-sc7280.c
@@ -118,12 +118,15 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev)
goto destroy_pm_clk;
}
- lpass_regmap_config.name = "qdsp6ss";
- desc = &lpass_qdsp6ss_sc7280_desc;
-
- ret = qcom_cc_probe_by_index(pdev, 0, desc);
- if (ret)
- goto destroy_pm_clk;
+ if (!of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
+ lpass_regmap_config.name = "qdsp6ss";
+ desc = &lpass_qdsp6ss_sc7280_desc;
+
+ ret = qcom_cc_probe_by_index(pdev, 0, desc);
+ if (ret)
+ goto destroy_pm_clk;
+ }
+ }
lpass_regmap_config.name = "top_cc";
desc = &lpass_cc_top_sc7280_desc;
--
2.7.4
The clock gating control for TX/RX/WSA core bus clocks would be required
to be reset(moved from hardware control) from audio core driver. Thus
add the support for the reset clocks in audioreach based clock driver.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Tested-by: Mohammad Rafi Shaik <[email protected]>
---
drivers/clk/qcom/lpasscc-sc7280.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c
index e1af32c..1efb72d 100644
--- a/drivers/clk/qcom/lpasscc-sc7280.c
+++ b/drivers/clk/qcom/lpasscc-sc7280.c
@@ -12,10 +12,12 @@
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
+#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
#include "clk-regmap.h"
#include "clk-branch.h"
#include "common.h"
+#include "reset.h"
static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
.halt_reg = 0x0,
@@ -102,6 +104,18 @@ static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = {
.num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks),
};
+static const struct qcom_reset_map lpass_cc_sc7280_resets[] = {
+ [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
+ [LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 },
+ [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
+};
+
+static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = {
+ .config = &lpass_regmap_config,
+ .resets = lpass_cc_sc7280_resets,
+ .num_resets = ARRAY_SIZE(lpass_cc_sc7280_resets),
+};
+
static int lpass_cc_sc7280_probe(struct platform_device *pdev)
{
const struct qcom_cc_desc *desc;
@@ -125,7 +139,6 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev)
ret = qcom_cc_probe_by_index(pdev, 0, desc);
if (ret)
goto destroy_pm_clk;
- }
}
lpass_regmap_config.name = "top_cc";
@@ -135,6 +148,15 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev)
if (ret)
goto destroy_pm_clk;
+ if (of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
+ lpass_regmap_config.name = "reset_cgcr";
+ desc = &lpass_audio_cc_reset_sc7280_desc;
+
+ ret = qcom_cc_probe_by_index(pdev, 2, desc);
+ if (ret)
+ goto destroy_pm_clk;
+ }
+
return 0;
destroy_pm_clk:
--
2.7.4
Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
for audioreach based SC7280 platforms.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Tested-by: Mohammad Rafi Shaik <[email protected]>
---
.../devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
index 97c6bd9..054c496 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
@@ -31,15 +31,20 @@ properties:
'#clock-cells':
const: 1
+ '#reset-cells':
+ const: 1
+
reg:
items:
- description: LPASS qdsp6ss register
- description: LPASS top-cc register
+ - description: LPASS reset-cgcr register
reg-names:
items:
- const: qdsp6ss
- const: top_cc
+ - const: reset_cgcr
qcom,adsp-pil-mode:
description:
@@ -62,11 +67,14 @@ examples:
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
clock-controller@3000000 {
compatible = "qcom,sc7280-lpasscc";
- reg = <0x03000000 0x40>, <0x03c04000 0x4>;
- reg-names = "qdsp6ss", "top_cc";
+ reg = <0x03000000 0x40>,
+ <0x03c04000 0x4>,
+ <0x032a9000 0x1000>;
+ reg-names = "qdsp6ss", "top_cc", "reset_cgcr";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
qcom,adsp-pil-mode;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
...
--
2.7.4
When this property is set, the remoteproc is used to boot the
LPASS and therefore qdsp6ss clocks would be used to bring LPASS
out of reset, hence they are directly controlled by the remoteproc.
This is a cleanup done to handle overlap of regmap of lpasscc
and adsp remoteproc blocks.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Tested-by: Mohammad Rafi Shaik <[email protected]>
---
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
index 6151fde..97c6bd9 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
@@ -41,6 +41,12 @@ properties:
- const: qdsp6ss
- const: top_cc
+ qcom,adsp-pil-mode:
+ description:
+ Indicates if the LPASS would be brought out of reset using
+ remoteproc peripheral loader.
+ type: boolean
+
required:
- compatible
- reg
@@ -60,6 +66,7 @@ examples:
reg-names = "qdsp6ss", "top_cc";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
+ qcom,adsp-pil-mode;
#clock-cells = <1>;
};
...
--
2.7.4