2023-03-06 13:56:01

by Abel Vesa

Subject: [PATCH v4] soc: qcom: llcc: Fix slice configuration values for SC8280XP

The slice IDs for CVPFW, CPUSS1 and CPUWHT currently overflow the 32bit
LLCC config registers, which means it is writing beyond the upper limit
of the ATTR0_CFGn and ATTR1_CFGn range of registers. But the most obvious
impact is the fact that the mentioned slices do not get configured at all,
which will result in reduced performance. Fix that by using the slice ID
values taken from the latest LLCC SC table.

Fixes: ec69dfbdc426 ("soc: qcom: llcc: Add sc8180x and sc8280xp configurations")
Cc: [email protected] # 5.19+
Signed-off-by: Abel Vesa <[email protected]>
Tested-by: Juerg Haefliger <[email protected]>
Reviewed-by: Sai Prakash Ranjan <[email protected]>
Acked-by: Konrad Dybcio <[email protected]>
Reviewed-by: Johan Hovold <[email protected]>
---

The v3 is here:
https://lore.kernel.org/all/[email protected]/

Changes since v3:
* explicitly mentioned in the commit message the fact that some random
registers might get written and the fact that there is an impact
on performance.
* Added Johan's R-b tag

Changes since v2:
* specifically mentioned the 3 slice IDs that are being fixed and
what is happening without this patch
* added stabke Cc line
* added Juerg's T-b tag
* added Sai's R-b tag
* added Konrad's A-b tag

Changes since v1:
* dropped the LLCC_GPU and LLCC_WRCACHE max_cap changes
* took the new values from documentatio this time rather than
downstream kernel

drivers/soc/qcom/llcc-qcom.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 23ce2f78c4ed..26efe12012a0 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -191,9 +191,9 @@ static const struct llcc_slice_config sc8280xp_data[] = {
{ LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
{ LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 },
{ LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
- { LLCC_CVPFW, 32, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
- { LLCC_CPUSS1, 33, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
- { LLCC_CPUHWT, 36, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
+ { LLCC_CVPFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
+ { LLCC_CPUSS1, 3, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
+ { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
};

static const struct llcc_slice_config sdm845_data[] = {
--
2.34.1

2023-03-07 04:17:13

by Bjorn Andersson

Subject: Re: [PATCH v4] soc: qcom: llcc: Fix slice configuration values for SC8280XP

On Mon, 6 Mar 2023 15:55:27 +0200, Abel Vesa wrote:
> The slice IDs for CVPFW, CPUSS1 and CPUWHT currently overflow the 32bit
> LLCC config registers, which means it is writing beyond the upper limit
> of the ATTR0_CFGn and ATTR1_CFGn range of registers. But the most obvious
> impact is the fact that the mentioned slices do not get configured at all,
> which will result in reduced performance. Fix that by using the slice ID
> values taken from the latest LLCC SC table.
>
> [...]

Applied, thanks!

[1/1] soc: qcom: llcc: Fix slice configuration values for SC8280XP
commit: 77bf4b3ed42e31d29b255fcd6530fb7a1e217e89

Best regards,
--
Bjorn Andersson <[email protected]>