2023-03-09 14:36:32

by Bartosz Golaszewski

Subject: [PATCH 0/2] arm64: qcom: sa8155-adp: enable the high-speed UART for GNSS

From: Bartosz Golaszewski <[email protected]>

Add the relevant QUPv3 node to SoC dtsi and enable it in the board dts for
sa8155p-adp.

Bartosz Golaszewski (2):
arm64: dts: sm8150: add the QUPv3 high-speed UART node
arm64: dts: qcom: sa8155p-adp: enable the GNSS high-speed UART

arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 5 +++++
arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 +++++++++++++++++++++
2 files changed, 26 insertions(+)

--
2.37.2

2023-03-09 14:36:36

by Bartosz Golaszewski

Subject: [PATCH 1/2] arm64: dts: sm8150: add the QUPv3 high-speed UART node

From: Bartosz Golaszewski <[email protected]>

Add the high-speed UART node to the dtsi for sm8150.

Signed-off-by: Bartosz Golaszewski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 13e0ce828606..cd0351a33516 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1334,6 +1334,20 @@ spi9: spi@a84000 {
status = "disabled";
};

+ uart9: serial@a8c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00a84000 0x0 0x4000>;
+ reg-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+ pinctrl-0 = <&qup_uart9_default>;
+ pinctrl-names = "default";
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
i2c10: i2c@a88000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a88000 0 0x4000>;
@@ -2425,6 +2439,13 @@ qup_spi9_default: qup-spi9-default-state {
bias-disable;
};

+ qup_uart9_default: qup-uart9-default-state {
+ pins = "gpio41", "gpio42";
+ function = "qup9";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
qup_i2c10_default: qup-i2c10-default-state {
pins = "gpio9", "gpio10";
function = "qup10";
--
2.37.2

2023-03-09 14:36:39

by Bartosz Golaszewski

Subject: [PATCH 2/2] arm64: dts: qcom: sa8155p-adp: enable the GNSS high-speed UART

From: Bartosz Golaszewski <[email protected]>

Enable the high-speed UART port that's connected to the GNSS controller
on the board.

Signed-off-by: Bartosz Golaszewski <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
index 459384ec8f23..339fea522509 100644
--- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
@@ -17,6 +17,7 @@ / {

aliases {
serial0 = &uart2;
+ serial1 = &uart9;
};

chosen {
@@ -400,6 +401,10 @@ &uart2 {
status = "okay";
};

+&uart9 {
+ status = "okay";
+};
+
&ufs_mem_hc {
status = "okay";

--
2.37.2

2023-03-15 23:32:25

by Bjorn Andersson

Subject: Re: [PATCH 0/2] arm64: qcom: sa8155-adp: enable the high-speed UART for GNSS

On Thu, 9 Mar 2023 15:35:49 +0100, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add the relevant QUPv3 node to SoC dtsi and enable it in the board dts for
> sa8155p-adp.
>
> Bartosz Golaszewski (2):
> arm64: dts: sm8150: add the QUPv3 high-speed UART node
> arm64: dts: qcom: sa8155p-adp: enable the GNSS high-speed UART
>
> [...]

Applied, thanks!

[1/2] arm64: dts: sm8150: add the QUPv3 high-speed UART node
commit: 10d900a834da29cf753f1e45f66982e322a177c1
[2/2] arm64: dts: qcom: sa8155p-adp: enable the GNSS high-speed UART
commit: d97ba0b040b1aee7c2a7a7155b7752413a965d1f

Best regards,
--
Bjorn Andersson <[email protected]>