Add basic support for managing "pcie-mem" interconnect path by setting
a low constraint before enabling clocks and updating it after the link
is up based on link speed and width the device got enumerated.
changes from v8:
- Added cpu to pcie path in dtsi and in dtsi binding.
changes from v7:
- setting icc bw to '0' in disable resources as suggested by mani.
changes from v6:
- addressed the comments as suggested by mani.
changes from v5:
- addressed the comments by mani.
changes from v4:
- rebased with linux-next.
- Added comments as suggested by mani.
- removed the arm: dts: qcom: sdx55: Add interconnect path
as that patch is already applied.
changes from v3:
- ran make DT_CHECKER_FLAGS=-m dt_binding_check and fixed
errors.
- Added macros in the qcom ep driver patch as suggested by Dmitry
changes from v2:
- changed the logic for getting speed and width as suggested
by bjorn.
- fixed compilation errors.
Krishna chaitanya chundru (4):
dt-bindings: PCI: qcom: ep: Add interconnects path
arm: dts: qcom: sdx65: Add PCIe interconnect path
arm: dts: qcom: sdx55: Add CPU PCIe interconnect path
PCI: qcom-ep: Add ICC bandwidth voting support
.../devicetree/bindings/pci/qcom,pcie-ep.yaml | 15 +++++
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 5 +-
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 4 ++
drivers/pci/controller/dwc/pcie-qcom-ep.c | 72 ++++++++++++++++++++++
4 files changed, 94 insertions(+), 2 deletions(-)
--
2.7.4
Some platforms may not boot if a device driver doesn't
initialize the interconnect path. Mostly it is handled
by the bootloader but we have starting to see cases
where bootloader simply ignores them.
Add the "pcie-mem" & "cpu-pcie" interconnect path as a required
property to the bindings.
Signed-off-by: Krishna chaitanya chundru <[email protected]>
Acked-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index 8111122..e553341 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -71,6 +71,14 @@ properties:
description: GPIO used as WAKE# output signal
maxItems: 1
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: pcie-mem
+ - const: cpu-pcie
+
resets:
maxItems: 1
@@ -98,6 +106,8 @@ required:
- interrupts
- interrupt-names
- reset-gpios
+ - interconnects
+ - interconnect-names
- resets
- reset-names
- power-domains
@@ -167,7 +177,9 @@ examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdx55.h>
#include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,sdx55.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+
pcie_ep: pcie-ep@1c00000 {
compatible = "qcom,sdx55-pcie-ep";
reg = <0x01c00000 0x3000>,
@@ -194,6 +206,9 @@ examples:
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global", "doorbell";
+ interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,
+ <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_PCIE_BCR>;
--
2.7.4
Add pcie-mem & cpu-pcie interconnect path to sdx65 platform.
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Krishna chaitanya chundru <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
index 1a35830..69fe7e5 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
@@ -332,6 +332,10 @@
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global", "doorbell";
+ interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>,
+ <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_PCIE_0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
resets = <&gcc GCC_PCIE_BCR>;
reset-names = "core";
--
2.7.4