2023-09-12 07:37:56

by Jisheng Zhang

[permalink] [raw]
Subject: [PATCH v3] riscv: errata: fix T-Head dcache.cva encoding

From: Icenowy Zheng <[email protected]>

The dcache.cva encoding shown in the comments are wrong, it's for
dcache.cval1 (which is restricted to L1) instead.

Fix this in the comment and in the hardcoded instruction.

Signed-off-by: Icenowy Zheng <[email protected]>
Tested-by: Sergey Matyukevich <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
Tested-by: Drew Fustini <[email protected]>
---

This is a renew of Icenowy patch series[1], patch1 is necessary to
make T-Head C910 powered SoCs CMO work correctly.

Link: https://lore.kernel.org/linux-riscv/[email protected]/ [1]

Since v2:
- rebase on linux 6.6-rc1
- collect Tested-by tag
- remove patch2 since I want patch1 to be applied as fix for
linux-6.6. patch2 will be sent separately.

Since v1:
- rebase on linux 6.5-rc7
- collect Reviewed-by tag


arch/riscv/include/asm/errata_list.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index e2ecd01bfac7..b55b434f0059 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -105,7 +105,7 @@ asm volatile(ALTERNATIVE( \
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
* 0000001 01001 rs1 000 00000 0001011
* dcache.cva rs1 (clean, virtual address)
- * 0000001 00100 rs1 000 00000 0001011
+ * 0000001 00101 rs1 000 00000 0001011
*
* dcache.cipa rs1 (clean then invalidate, physical address)
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
@@ -118,7 +118,7 @@ asm volatile(ALTERNATIVE( \
* 0000000 11001 00000 000 00000 0001011
*/
#define THEAD_inval_A0 ".long 0x0265000b"
-#define THEAD_clean_A0 ".long 0x0245000b"
+#define THEAD_clean_A0 ".long 0x0255000b"
#define THEAD_flush_A0 ".long 0x0275000b"
#define THEAD_SYNC_S ".long 0x0190000b"

--
2.40.1


Subject: Re: [PATCH v3] riscv: errata: fix T-Head dcache.cva encoding

Hello:

This patch was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <[email protected]>:

On Tue, 12 Sep 2023 15:24:10 +0800 you wrote:
> From: Icenowy Zheng <[email protected]>
>
> The dcache.cva encoding shown in the comments are wrong, it's for
> dcache.cval1 (which is restricted to L1) instead.
>
> Fix this in the comment and in the hardcoded instruction.
>
> [...]

Here is the summary with links:
- [v3] riscv: errata: fix T-Head dcache.cva encoding
https://git.kernel.org/riscv/c/8eb8fe67e2c8

You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html


2023-09-13 11:10:22

by Palmer Dabbelt

[permalink] [raw]
Subject: Re: [PATCH v3] riscv: errata: fix T-Head dcache.cva encoding


On Tue, 12 Sep 2023 15:24:10 +0800, Jisheng Zhang wrote:
> The dcache.cva encoding shown in the comments are wrong, it's for
> dcache.cval1 (which is restricted to L1) instead.
>
> Fix this in the comment and in the hardcoded instruction.
>
>

Applied, thanks!

[1/1] riscv: errata: fix T-Head dcache.cva encoding
https://git.kernel.org/palmer/c/8eb8fe67e2c8

Best regards,
--
Palmer Dabbelt <[email protected]>