2023-09-13 19:21:34

by MD Danish Anwar

Subject: [PATCH net-next v3 1/2] dt-bindings: net: Add documentation for Half duplex support.

In order to support half-duplex operation at 10M and 100M link speeds, the
PHY collision detection signal (COL) should be routed to ICSSG
GPIO pin (PRGx_PRU0/1_GPI10) so that firmware can detect collision signal
and apply the CSMA/CD algorithm applicable for half duplex operation. A DT
property, "ti,half-duplex-capable" is introduced for this purpose. If
board has PHY COL pin conencted to PRGx_PRU1_GPIO10, this DT property can
be added to eth node of ICSSG, MII port to support half duplex operation at
that port.

Reviewed-by: Roger Quadros <[email protected]>
Signed-off-by: MD Danish Anwar <[email protected]>
---
Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml
index 836d2d60e87d..229c8f32019f 100644
--- a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml
+++ b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml
@@ -107,6 +107,13 @@ properties:
phandle to system controller node and register offset
to ICSSG control register for RGMII transmit delay

+ ti,half-duplex-capable:
+ type: boolean
+ description:
+ Indicates that the PHY output pin COL is routed to ICSSG GPIO pin
+ (PRGx_PRU0/1_GPIO10) as input so that the ICSSG MII port is
+ capable of half duplex operations.
+
required:
- reg
anyOf:
--
2.34.1

2023-09-14 17:41:03

by Rob Herring (Arm)

Subject: Re: [PATCH net-next v3 1/2] dt-bindings: net: Add documentation for Half duplex support.

On Wed, 13 Sep 2023 14:40:10 +0530, MD Danish Anwar wrote:
> In order to support half-duplex operation at 10M and 100M link speeds, the
> PHY collision detection signal (COL) should be routed to ICSSG
> GPIO pin (PRGx_PRU0/1_GPI10) so that firmware can detect collision signal
> and apply the CSMA/CD algorithm applicable for half duplex operation. A DT
> property, "ti,half-duplex-capable" is introduced for this purpose. If
> board has PHY COL pin conencted to PRGx_PRU1_GPIO10, this DT property can
> be added to eth node of ICSSG, MII port to support half duplex operation at
> that port.
>
> Reviewed-by: Roger Quadros <[email protected]>
> Signed-off-by: MD Danish Anwar <[email protected]>
> ---
> Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>

Reviewed-by: Rob Herring <[email protected]>