2023-10-11 11:19:50

by Mrinmay Sarkar

Subject: [PATCH v2 1/4] dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC

Add devicetree bindings support for SA8775P SoC.
Define reg and interrupt per platform.

Signed-off-by: Mrinmay Sarkar <[email protected]>
---
.../devicetree/bindings/pci/qcom,pcie-ep.yaml | 131 +++++++++++++++++----
1 file changed, 109 insertions(+), 22 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index a223ce0..8f219a6e 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -13,36 +13,28 @@ properties:
compatible:
oneOf:
- enum:
+ - qcom,sa8775p-pcie-ep
- qcom,sdx55-pcie-ep
- qcom,sm8450-pcie-ep
- items:
+ - const: qcom,sa8775p-pcie-ep
- const: qcom,sdx65-pcie-ep
- const: qcom,sdx55-pcie-ep

reg:
- items:
- - description: Qualcomm-specific PARF configuration registers
- - description: DesignWare PCIe registers
- - description: External local bus interface registers
- - description: Address Translation Unit (ATU) registers
- - description: Memory region used to map remote RC address space
- - description: BAR memory region
+ minItems: 6
+ maxItems: 7

reg-names:
- items:
- - const: parf
- - const: dbi
- - const: elbi
- - const: atu
- - const: addr_space
- - const: mmio
+ minItems: 6
+ maxItems: 7

clocks:
- minItems: 7
+ minItems: 5
maxItems: 8

clock-names:
- minItems: 7
+ minItems: 5
maxItems: 8

qcom,perst-regs:
@@ -57,14 +49,12 @@ properties:
- description: Perst separation enable offset

interrupts:
- items:
- - description: PCIe Global interrupt
- - description: PCIe Doorbell interrupt
+ minItems: 2
+ maxItems: 3

interrupt-names:
- items:
- - const: global
- - const: doorbell
+ minItems: 2
+ maxItems: 3

reset-gpios:
description: GPIO used as PERST# input signal
@@ -122,6 +112,51 @@ allOf:
compatible:
contains:
enum:
+ - qcom,sa8775p-pcie-ep
+ then:
+ properties:
+ reg:
+ items:
+ - description: Qualcomm-specific PARF configuration registers
+ - description: DesignWare PCIe registers
+ - description: External local bus interface registers
+ - description: Address Translation Unit (ATU) registers
+ - description: Memory region used to map remote RC address space
+ - description: BAR memory region
+ - description: DMA register space
+ reg-names:
+ items:
+ - const: parf
+ - const: dbi
+ - const: elbi
+ - const: atu
+ - const: addr_space
+ - const: mmio
+ - const: dma
+ else:
+ properties:
+ reg:
+ items:
+ - description: Qualcomm-specific PARF configuration registers
+ - description: DesignWare PCIe registers
+ - description: External local bus interface registers
+ - description: Address Translation Unit (ATU) registers
+ - description: Memory region used to map remote RC address space
+ - description: BAR memory region
+ reg-names:
+ items:
+ - const: parf
+ - const: dbi
+ - const: elbi
+ - const: atu
+ - const: addr_space
+ - const: mmio
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,sdx55-pcie-ep
then:
properties:
@@ -173,6 +208,58 @@ allOf:
- const: ddrss_sf_tbu
- const: aggre_noc_axi

+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sa8775-pcie-ep
+ then:
+ properties:
+ clocks:
+ items:
+ - description: PCIe Auxiliary clock
+ - description: PCIe CFG AHB clock
+ - description: PCIe Master AXI clock
+ - description: PCIe Slave AXI clock
+ - description: PCIe Slave Q2A AXI clock
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg
+ - const: bus_master
+ - const: bus_slave
+ - const: slave_q2a
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sa8775p-pcie-ep
+ then:
+ properties:
+ interrupts:
+ items:
+ - description: PCIe Global interrupt
+ - description: PCIe Doorbell interrupt
+ - description: DMA interrupt
+ interrupt-names:
+ items:
+ - const: global
+ - const: doorbell
+ - const: dma
+ else:
+ properties:
+ interrupts:
+ items:
+ - description: PCIe Global interrupt
+ - description: PCIe Doorbell interrupt
+ interrupt-names:
+ items:
+ - const: global
+ - const: doorbell
+
unevaluatedProperties: false

examples:
--
2.7.4

2023-10-11 18:31:03

by Krzysztof Kozlowski

Subject: Re: [PATCH v2 1/4] dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC

On 11/10/2023 13:18, Mrinmay Sarkar wrote:
> Add devicetree bindings support for SA8775P SoC.
> Define reg and interrupt per platform.
>
> Signed-off-by: Mrinmay Sarkar <[email protected]>
> ---
> .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 131 +++++++++++++++++----
> 1 file changed, 109 insertions(+), 22 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> index a223ce0..8f219a6e 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> @@ -13,36 +13,28 @@ properties:
> compatible:
> oneOf:
> - enum:
> + - qcom,sa8775p-pcie-ep
> - qcom,sdx55-pcie-ep
> - qcom,sm8450-pcie-ep
> - items:
> + - const: qcom,sa8775p-pcie-ep

So you broke all existing users.

It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).



Best regards,
Krzysztof