This series adds the relavent DT bindings, new compatible string,
add support to EPF driver and add EP PCIe node in dtsi file for
ep pcie0 controller.
v5 -> v6:
- update cover letter.
v4 -> v5:
- add maxItems to the respective field to constrain io space and
interrupt in all variants.
v3 -> v4:
- add maxItems field in dt bindings
- update comment in patch2
- dropped PHY driver patch as it is already applied [1]
- update comment in EPF driver patch
- update commect in dtsi and add iommus instead of iommu-map
[1] https://lore.kernel.org/all/[email protected]/
v2 -> v3:
- removed if/then schemas, added minItems for reg,
reg-bnames, interrupt and interrupt-names instead.
- adding qcom,sa8775p-pcie-ep compitable for sa8775p
as we have some specific change to add.
- reusing sm8450's pcs_misc num table as it is same as sa8775p.
used appropriate namespace for pcs.
- remove const from sa8775p_header as kernel test robot
throwing some warnings due to this.
- remove fallback compatiable as we are adding compatiable for sa8775p.
v1 -> v2:
- update description for dma
- Reusing qcom,sdx55-pcie-ep compatibe so remove compaitable
for sa8775p
- sort the defines in phy header file and remove extra defines
- add const in return type pci_epf_header and remove MHI_EPF_USE_DMA
flag as hdma patch is not ready
- add fallback compatiable as qcom,sdx55-pcie-ep, add iommu property
Mrinmay Sarkar (4):
dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC
PCI: qcom-ep: Add support for SA8775P SOC
PCI: epf-mhi: Add support for SA8775P
arm64: dts: qcom: sa8775p: Add ep pcie0 controller node
.../devicetree/bindings/pci/qcom,pcie-ep.yaml | 64 +++++++++++++++++++++-
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 46 ++++++++++++++++
drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
drivers/pci/endpoint/functions/pci-epf-mhi.c | 17 ++++++
4 files changed, 126 insertions(+), 2 deletions(-)
--
2.7.4
Add support for Qualcomm Snapdragon SA8775P SoC to the EPF driver.
Reusing DID (0x0306) for SA8775P and it supports HDMA. Currently,
it has no fixed PCI class, so it is being advertised as
"PCI_CLASS_OTHERS".
Signed-off-by: Mrinmay Sarkar <[email protected]>
---
drivers/pci/endpoint/functions/pci-epf-mhi.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c
index b7b9d3e..23ea94e 100644
--- a/drivers/pci/endpoint/functions/pci-epf-mhi.c
+++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c
@@ -114,6 +114,22 @@ static const struct pci_epf_mhi_ep_info sm8450_info = {
.flags = MHI_EPF_USE_DMA,
};
+static struct pci_epf_header sa8775p_header = {
+ .vendorid = PCI_VENDOR_ID_QCOM,
+ .deviceid = 0x0306, /* FIXME: Update deviceid for sa8775p EP */
+ .baseclass_code = PCI_CLASS_OTHERS,
+ .interrupt_pin = PCI_INTERRUPT_INTA,
+};
+
+static const struct pci_epf_mhi_ep_info sa8775p_info = {
+ .config = &mhi_v1_config,
+ .epf_header = &sa8775p_header,
+ .bar_num = BAR_0,
+ .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32,
+ .msi_count = 32,
+ .mru = 0x8000,
+};
+
struct pci_epf_mhi {
const struct pci_epc_features *epc_features;
const struct pci_epf_mhi_ep_info *info;
@@ -677,6 +693,7 @@ static int pci_epf_mhi_probe(struct pci_epf *epf,
}
static const struct pci_epf_device_id pci_epf_mhi_ids[] = {
+ { .name = "sa8775p", .driver_data = (kernel_ulong_t)&sa8775p_info },
{ .name = "sdx55", .driver_data = (kernel_ulong_t)&sdx55_info },
{ .name = "sm8450", .driver_data = (kernel_ulong_t)&sm8450_info },
{},
--
2.7.4
Add support for SA8775P SoC to the Qualcomm PCIe Endpoint Controller
driver. Adding new compatible string as it has different set of clocks
compare to other SOCs.
Signed-off-by: Mrinmay Sarkar <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 9e58f05..3a53d97 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -875,6 +875,7 @@ static void qcom_pcie_ep_remove(struct platform_device *pdev)
}
static const struct of_device_id qcom_pcie_ep_match[] = {
+ { .compatible = "qcom,sa8775p-pcie-ep", },
{ .compatible = "qcom,sdx55-pcie-ep", },
{ .compatible = "qcom,sm8450-pcie-ep", },
{ }
--
2.7.4
Add ep pcie dtsi node for pcie0 controller found on sa8775p platform.
It supports gen4 and x2 link width. Limiting the speed to Gen3 due to
stability issues.
Signed-off-by: Mrinmay Sarkar <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 46 +++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 13dd44d..7eab458 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3586,6 +3586,52 @@
status = "disabled";
};
+ pcie0_ep: pcie-ep@1c00000 {
+ compatible = "qcom,sa8775p-pcie-ep";
+ reg = <0x0 0x01c00000 0x0 0x3000>,
+ <0x0 0x40000000 0x0 0xf20>,
+ <0x0 0x40000f20 0x0 0xa8>,
+ <0x0 0x40001000 0x0 0x4000>,
+ <0x0 0x40200000 0x0 0x100000>,
+ <0x0 0x01c03000 0x0 0x1000>,
+ <0x0 0x40005000 0x0 0x2000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
+ "mmio", "dma";
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
+
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a";
+
+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "global", "doorbell", "dma";
+
+ interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ iommus = <&pcie_smmu 0x0000 0x7f>;
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "core";
+ power-domains = <&gcc PCIE_0_GDSC>;
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+ max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
+ num-lanes = <2>;
+
+ status = "disabled";
+ };
+
pcie0_phy: phy@1c04000 {
compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
reg = <0x0 0x1c04000 0x0 0x2000>;
--
2.7.4
On Tue, Oct 31, 2023 at 10:41:46AM +0530, Mrinmay Sarkar wrote:
"s/SOC/SoC" in subject.
> Add support for SA8775P SoC to the Qualcomm PCIe Endpoint Controller
> driver. Adding new compatible string as it has different set of clocks
> compare to other SOCs.
"compared to ther SoCs."
>
> Signed-off-by: Mrinmay Sarkar <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
- Mani
> ---
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index 9e58f05..3a53d97 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -875,6 +875,7 @@ static void qcom_pcie_ep_remove(struct platform_device *pdev)
> }
>
> static const struct of_device_id qcom_pcie_ep_match[] = {
> + { .compatible = "qcom,sa8775p-pcie-ep", },
> { .compatible = "qcom,sdx55-pcie-ep", },
> { .compatible = "qcom,sm8450-pcie-ep", },
> { }
> --
> 2.7.4
>
--
மணிவண்ணன் சதாசிவம்
On Tue, Oct 31, 2023 at 10:41:48AM +0530, Mrinmay Sarkar wrote:
> Add ep pcie dtsi node for pcie0 controller found on sa8775p platform.
> It supports gen4 and x2 link width. Limiting the speed to Gen3 due to
> stability issues.
>
> Signed-off-by: Mrinmay Sarkar <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
One question below:
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 46 +++++++++++++++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 13dd44d..7eab458 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -3586,6 +3586,52 @@
> status = "disabled";
> };
>
> + pcie0_ep: pcie-ep@1c00000 {
> + compatible = "qcom,sa8775p-pcie-ep";
> + reg = <0x0 0x01c00000 0x0 0x3000>,
> + <0x0 0x40000000 0x0 0xf20>,
> + <0x0 0x40000f20 0x0 0xa8>,
> + <0x0 0x40001000 0x0 0x4000>,
> + <0x0 0x40200000 0x0 0x100000>,
> + <0x0 0x01c03000 0x0 0x1000>,
> + <0x0 0x40005000 0x0 0x2000>;
> + reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
> + "mmio", "dma";
> +
> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
> +
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a";
> +
> + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupt-names = "global", "doorbell", "dma";
> +
> + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
> + interconnect-names = "pcie-mem", "cpu-pcie";
> +
> + iommus = <&pcie_smmu 0x0000 0x7f>;
SID is really 0?
- Mani
> + resets = <&gcc GCC_PCIE_0_BCR>;
> + reset-names = "core";
> + power-domains = <&gcc PCIE_0_GDSC>;
> + phys = <&pcie0_phy>;
> + phy-names = "pciephy";
> + max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
> + num-lanes = <2>;
> +
> + status = "disabled";
> + };
> +
> pcie0_phy: phy@1c04000 {
> compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
> reg = <0x0 0x1c04000 0x0 0x2000>;
> --
> 2.7.4
>
--
மணிவண்ணன் சதாசிவம்
On 11/1/2023 10:56 AM, Manivannan Sadhasivam wrote:
> On Tue, Oct 31, 2023 at 10:41:48AM +0530, Mrinmay Sarkar wrote:
>> Add ep pcie dtsi node for pcie0 controller found on sa8775p platform.
>> It supports gen4 and x2 link width. Limiting the speed to Gen3 due to
>> stability issues.
>>
>> Signed-off-by: Mrinmay Sarkar <[email protected]>
> Reviewed-by: Manivannan Sadhasivam <[email protected]>
>
> One question below:
>
>> ---
>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 46 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 46 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> index 13dd44d..7eab458 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> @@ -3586,6 +3586,52 @@
>> status = "disabled";
>> };
>>
>> + pcie0_ep: pcie-ep@1c00000 {
>> + compatible = "qcom,sa8775p-pcie-ep";
>> + reg = <0x0 0x01c00000 0x0 0x3000>,
>> + <0x0 0x40000000 0x0 0xf20>,
>> + <0x0 0x40000f20 0x0 0xa8>,
>> + <0x0 0x40001000 0x0 0x4000>,
>> + <0x0 0x40200000 0x0 0x100000>,
>> + <0x0 0x01c03000 0x0 0x1000>,
>> + <0x0 0x40005000 0x0 0x2000>;
>> + reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
>> + "mmio", "dma";
>> +
>> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
>> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
>> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
>> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
>> +
>> + clock-names = "aux",
>> + "cfg",
>> + "bus_master",
>> + "bus_slave",
>> + "slave_q2a";
>> +
>> + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + interrupt-names = "global", "doorbell", "dma";
>> +
>> + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
>> + interconnect-names = "pcie-mem", "cpu-pcie";
>> +
>> + iommus = <&pcie_smmu 0x0000 0x7f>;
> SID is really 0?
>
> - Mani
Yes Mani, SA877P has SID 0x0 for pcie 0 controller and 0x80 for pcie 1
controller.
> --Mrinmay
>
>> + resets = <&gcc GCC_PCIE_0_BCR>;
>> + reset-names = "core";
>> + power-domains = <&gcc PCIE_0_GDSC>;
>> + phys = <&pcie0_phy>;
>> + phy-names = "pciephy";
>> + max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
>> + num-lanes = <2>;
>> +
>> + status = "disabled";
>> + };
>> +
>> pcie0_phy: phy@1c04000 {
>> compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
>> reg = <0x0 0x1c04000 0x0 0x2000>;
>> --
>> 2.7.4
>>
On Tue, Oct 31, 2023 at 10:41:47AM +0530, Mrinmay Sarkar wrote:
> Add support for Qualcomm Snapdragon SA8775P SoC to the EPF driver.
> Reusing DID (0x0306) for SA8775P and it supports HDMA. Currently,
You should state why you are reusing the "PID" and whether it is going to be
updated in the future or not.
> it has no fixed PCI class, so it is being advertised as
> "PCI_CLASS_OTHERS".
>
> Signed-off-by: Mrinmay Sarkar <[email protected]>
With the above mentioned change,
Reviewed-by: Manivannan Sadhasivam <[email protected]>
- Mani
> ---
> drivers/pci/endpoint/functions/pci-epf-mhi.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c
> index b7b9d3e..23ea94e 100644
> --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c
> +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c
> @@ -114,6 +114,22 @@ static const struct pci_epf_mhi_ep_info sm8450_info = {
> .flags = MHI_EPF_USE_DMA,
> };
>
> +static struct pci_epf_header sa8775p_header = {
> + .vendorid = PCI_VENDOR_ID_QCOM,
> + .deviceid = 0x0306, /* FIXME: Update deviceid for sa8775p EP */
> + .baseclass_code = PCI_CLASS_OTHERS,
> + .interrupt_pin = PCI_INTERRUPT_INTA,
> +};
> +
> +static const struct pci_epf_mhi_ep_info sa8775p_info = {
> + .config = &mhi_v1_config,
> + .epf_header = &sa8775p_header,
> + .bar_num = BAR_0,
> + .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32,
> + .msi_count = 32,
> + .mru = 0x8000,
> +};
> +
> struct pci_epf_mhi {
> const struct pci_epc_features *epc_features;
> const struct pci_epf_mhi_ep_info *info;
> @@ -677,6 +693,7 @@ static int pci_epf_mhi_probe(struct pci_epf *epf,
> }
>
> static const struct pci_epf_device_id pci_epf_mhi_ids[] = {
> + { .name = "sa8775p", .driver_data = (kernel_ulong_t)&sa8775p_info },
> { .name = "sdx55", .driver_data = (kernel_ulong_t)&sdx55_info },
> { .name = "sm8450", .driver_data = (kernel_ulong_t)&sm8450_info },
> {},
> --
> 2.7.4
>
>
--
மணிவண்ணன் சதாசிவம்