Hello,
This patchset adds UFS controller support for HiSilicon HI3670 SoC.
HI3760 SoC is very similar to HI3660 SoC with almost same IPs, hence
the same driver is extended to provide UFS support. Only major difference
is the PHY. HI3670 has 10nm PHY, hence that parameter is used to
distinguish the difference between two in driver.
Thanks,
Mani
Changes in v2:
As per Rob's review:
* Removed interrupt-parent property from binding.
* Fixed the bindings patch commit message.
Manivannan Sadhasivam (3):
dt-bindings: ufs: Add HI3670 UFS controller binding
arm64: dts: hisilicon: hi3670: Add UFS controller support
scsi: ufs: Add HI3670 SoC UFS driver support
.../devicetree/bindings/ufs/ufs-hisi.txt | 5 +-
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 18 +++
drivers/scsi/ufs/ufs-hisi.c | 127 +++++++++++++++---
drivers/scsi/ufs/ufs-hisi.h | 4 +
4 files changed, 130 insertions(+), 24 deletions(-)
--
2.17.1
Add devicetree binding for HI3670 UFS controller. HI3760 SoC is very
similar to HI3660 SoC with almost same IPs. Only major difference in terms
of UFS is the PHY. HI3670 has 10nm PHY. But since the original driver
(HI3660 UFS) cannot make HI3670 UFS functional, a separate compatible
is added for HI3670 without any fallback.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt
index a48c44817367..0b83df1a5418 100644
--- a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt
+++ b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt
@@ -6,9 +6,10 @@ Each UFS Host Controller should have its own node.
Required properties:
- compatible : compatible list, contains one of the following -
"hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs
- host controller present on Hi36xx chipset.
+ host controller present on Hi3660 chipset.
+ "hisilicon,hi3670-ufs", "jedec,ufs-2.1" for hisi ufs
+ host controller present on Hi3670 chipset.
- reg : should contain UFS register address space & UFS SYS CTRL register address,
-- interrupt-parent : interrupt device
- interrupts : interrupt number
- clocks : List of phandle and clock specifier pairs
- clock-names : List of clock input name strings sorted in the same
--
2.17.1
Add UFS controller support for HiSilicon HI3670 SoC.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 6ccdf5040ffd..285219dd657f 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -654,6 +654,24 @@
clock-names = "apb_pclk";
};
+ /* UFS */
+ ufs: ufs@ff3c0000 {
+ compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
+ /* 0: HCI standard */
+ /* 1: UFS SYS CTRL */
+ reg = <0x0 0xff3c0000 0x0 0x1000>,
+ <0x0 0xff3e0000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
+ <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
+ clock-names = "ref_clk", "phy_clk";
+ freq-table-hz = <0 0>, <0 0>;
+ /* offset: 0x84; bit: 12 */
+ resets = <&crg_rst 0x84 12>;
+ reset-names = "rst";
+ };
+
/* SD */
dwmmc1: dwmmc1@ff37f000 {
compatible = "hisilicon,hi3670-dw-mshc";
--
2.17.1
Add HI3670 SoC UFS driver support by extending the common ufs-hisi
driver. One major difference between HI3660 ad HI3670 SoCs interms of
UFS is the PHY. HI3670 has a 10nm variant PHY and hence this parameter is
used to distinguish the configuration.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/scsi/ufs/ufs-hisi.c | 127 +++++++++++++++++++++++++++++-------
drivers/scsi/ufs/ufs-hisi.h | 4 ++
2 files changed, 109 insertions(+), 22 deletions(-)
diff --git a/drivers/scsi/ufs/ufs-hisi.c b/drivers/scsi/ufs/ufs-hisi.c
index 452e19f8fb47..f2d3df357a97 100644
--- a/drivers/scsi/ufs/ufs-hisi.c
+++ b/drivers/scsi/ufs/ufs-hisi.c
@@ -66,7 +66,7 @@ static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
return err;
}
-static void ufs_hi3660_clk_init(struct ufs_hba *hba)
+static void ufs_hisi_clk_init(struct ufs_hba *hba)
{
struct ufs_hisi_host *host = ufshcd_get_variant(hba);
@@ -80,7 +80,7 @@ static void ufs_hi3660_clk_init(struct ufs_hba *hba)
ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
}
-static void ufs_hi3660_soc_init(struct ufs_hba *hba)
+static void ufs_hisi_soc_init(struct ufs_hba *hba)
{
struct ufs_hisi_host *host = ufshcd_get_variant(hba);
u32 reg;
@@ -139,6 +139,7 @@ static void ufs_hi3660_soc_init(struct ufs_hba *hba)
static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
{
+ struct ufs_hisi_host *host = ufshcd_get_variant(hba);
int err;
uint32_t value;
uint32_t reg;
@@ -153,6 +154,14 @@ static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D);
/* MPHY CBOVRCTRL3 */
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1);
+
+ if (host->caps & UFS_HISI_CAP_PHY10nm) {
+ /* MPHY CBOVRCTRL4 */
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8127, 0x0), 0x98);
+ /* MPHY CBOVRCTRL5 */
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8128, 0x0), 0x1);
+ }
+
/* Unipro VS_MphyCfgUpdt */
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
/* MPHY RXOVRCTRL4 rx0 */
@@ -173,10 +182,21 @@ static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8113, 0x0), 0x1);
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
- /* Tactive RX */
- ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7);
- /* Tactive RX */
- ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7);
+ if (host->caps & UFS_HISI_CAP_PHY10nm) {
+ /* RX_Hibern8Time_Capability*/
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x4), 0xA);
+ /* RX_Hibern8Time_Capability*/
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x5), 0xA);
+ /* RX_Min_ActivateTime */
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x4), 0xA);
+ /* RX_Min_ActivateTime*/
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x5), 0xA);
+ } else {
+ /* Tactive RX */
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7);
+ /* Tactive RX */
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7);
+ }
/* Gear3 Synclength */
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x4), 0x4F);
@@ -208,7 +228,8 @@ static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
if (err)
dev_err(hba->dev, "ufs_hisi_check_hibern8 error\n");
- ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
+ if (!(host->caps & UFS_HISI_CAP_PHY10nm))
+ ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
/* disable auto H8 */
reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
@@ -253,7 +274,7 @@ static int ufs_hisi_link_startup_post_change(struct ufs_hba *hba)
return 0;
}
-static int ufs_hi3660_link_startup_notify(struct ufs_hba *hba,
+static int ufs_hisi_link_startup_notify(struct ufs_hba *hba,
enum ufs_notify_change_status status)
{
int err = 0;
@@ -391,6 +412,28 @@ static void ufs_hisi_set_dev_cap(struct ufs_hisi_dev_params *hisi_param)
static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
{
+ struct ufs_hisi_host *host = ufshcd_get_variant(hba);
+
+ if (host->caps & UFS_HISI_CAP_PHY10nm) {
+ /*
+ * Boston platform need to set SaveConfigTime to 0x13,
+ * and change sync length to maximum value
+ */
+ /* VS_DebugSaveConfigTime */
+ ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0xD0A0), 0x13);
+ /* g1 sync length */
+ ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1552), 0x4f);
+ /* g2 sync length */
+ ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1554), 0x4f);
+ /* g3 sync length */
+ ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1556), 0x4f);
+ /* PA_Hibern8Time */
+ ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a7), 0xA);
+ /* PA_Tactivate */
+ ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a8), 0xA);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd085, 0x0), 0x01);
+ }
+
if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME) {
pr_info("ufs flash device must set VS_DebugSaveConfigTime 0x10\n");
/* VS_DebugSaveConfigTime */
@@ -429,7 +472,7 @@ static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
ufshcd_dme_set(hba, UIC_ARG_MIB(0xd046), 32767);
}
-static int ufs_hi3660_pwr_change_notify(struct ufs_hba *hba,
+static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
enum ufs_notify_change_status status,
struct ufs_pa_layer_attr *dev_max_params,
struct ufs_pa_layer_attr *dev_req_params)
@@ -567,25 +610,72 @@ static int ufs_hi3660_init(struct ufs_hba *hba)
return ret;
}
- ufs_hi3660_clk_init(hba);
+ ufs_hisi_clk_init(hba);
+
+ ufs_hisi_soc_init(hba);
+
+ return 0;
+}
+
+static int ufs_hi3670_init(struct ufs_hba *hba)
+{
+ int ret = 0;
+ struct device *dev = hba->dev;
+ struct ufs_hisi_host *host;
+
+ ret = ufs_hisi_init_common(hba);
+ if (ret) {
+ dev_err(dev, "%s: ufs common init fail\n", __func__);
+ return ret;
+ }
+
+ ufs_hisi_clk_init(hba);
+
+ ufs_hisi_soc_init(hba);
- ufs_hi3660_soc_init(hba);
+ /* Add cap for 10nm PHY variant on HI3670 SoC */
+ host = ufshcd_get_variant(hba);
+ host->caps |= UFS_HISI_CAP_PHY10nm;
return 0;
}
-static struct ufs_hba_variant_ops ufs_hba_hisi_vops = {
+static struct ufs_hba_variant_ops ufs_hba_hi3660_vops = {
.name = "hi3660",
.init = ufs_hi3660_init,
- .link_startup_notify = ufs_hi3660_link_startup_notify,
- .pwr_change_notify = ufs_hi3660_pwr_change_notify,
+ .link_startup_notify = ufs_hisi_link_startup_notify,
+ .pwr_change_notify = ufs_hisi_pwr_change_notify,
.suspend = ufs_hisi_suspend,
.resume = ufs_hisi_resume,
};
+static struct ufs_hba_variant_ops ufs_hba_hi3670_vops = {
+ .name = "hi3670",
+ .init = ufs_hi3670_init,
+ .link_startup_notify = ufs_hisi_link_startup_notify,
+ .pwr_change_notify = ufs_hisi_pwr_change_notify,
+ .suspend = ufs_hisi_suspend,
+ .resume = ufs_hisi_resume,
+};
+
+static const struct of_device_id ufs_hisi_of_match[] = {
+ { .compatible = "hisilicon,hi3660-ufs", .data = &ufs_hba_hi3660_vops },
+ { .compatible = "hisilicon,hi3670-ufs", .data = &ufs_hba_hi3670_vops },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, ufs_hisi_of_match);
+
static int ufs_hisi_probe(struct platform_device *pdev)
{
- return ufshcd_pltfrm_init(pdev, &ufs_hba_hisi_vops);
+ const struct of_device_id *of_id;
+ struct ufs_hba_variant_ops *vops;
+ struct device *dev = &pdev->dev;
+
+ of_id = of_match_node(ufs_hisi_of_match, dev->of_node);
+ vops = (struct ufs_hba_variant_ops *)of_id->data;
+
+ return ufshcd_pltfrm_init(pdev, vops);
}
static int ufs_hisi_remove(struct platform_device *pdev)
@@ -596,13 +686,6 @@ static int ufs_hisi_remove(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id ufs_hisi_of_match[] = {
- { .compatible = "hisilicon,hi3660-ufs" },
- {},
-};
-
-MODULE_DEVICE_TABLE(of, ufs_hisi_of_match);
-
static const struct dev_pm_ops ufs_hisi_pm_ops = {
.suspend = ufshcd_pltfrm_suspend,
.resume = ufshcd_pltfrm_resume,
diff --git a/drivers/scsi/ufs/ufs-hisi.h b/drivers/scsi/ufs/ufs-hisi.h
index 3df9cd7acc29..667dfe39b57e 100644
--- a/drivers/scsi/ufs/ufs-hisi.h
+++ b/drivers/scsi/ufs/ufs-hisi.h
@@ -91,6 +91,9 @@ enum {
#define UFS_HISI_LIMIT_HS_RATE PA_HS_MODE_B
#define UFS_HISI_LIMIT_DESIRED_MODE FAST
+#define UFS_HISI_CAP_RESERVED BIT(0)
+#define UFS_HISI_CAP_PHY10nm BIT(1)
+
struct ufs_hisi_host {
struct ufs_hba *hba;
void __iomem *ufs_sys_ctrl;
@@ -112,4 +115,5 @@ struct ufs_hisi_host {
ufs_sys_ctrl_writel((host), \
((~(mask)) & (ufs_sys_ctrl_readl((host), (reg)))), \
(reg))
+
#endif /* UFS_HISI_H_ */
--
2.17.1
On Sat, 5 Jan 2019 12:58:57 +0530, Manivannan Sadhasivam wrote:
> Add devicetree binding for HI3670 UFS controller. HI3760 SoC is very
> similar to HI3660 SoC with almost same IPs. Only major difference in terms
> of UFS is the PHY. HI3670 has 10nm PHY. But since the original driver
> (HI3660 UFS) cannot make HI3670 UFS functional, a separate compatible
> is added for HI3670 without any fallback.
>
> Signed-off-by: Manivannan Sadhasivam <[email protected]>
> ---
> Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
On Sat, Jan 05, 2019 at 12:58:59PM +0530, Manivannan Sadhasivam wrote:
> Add HI3670 SoC UFS driver support by extending the common ufs-hisi
> driver. One major difference between HI3660 ad HI3670 SoCs interms of
> UFS is the PHY. HI3670 has a 10nm variant PHY and hence this parameter is
> used to distinguish the configuration.
>
> Signed-off-by: Manivannan Sadhasivam <[email protected]>
Hello,
Ping on this patch!
Thanks,
Mani
> ---
> drivers/scsi/ufs/ufs-hisi.c | 127 +++++++++++++++++++++++++++++-------
> drivers/scsi/ufs/ufs-hisi.h | 4 ++
> 2 files changed, 109 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/scsi/ufs/ufs-hisi.c b/drivers/scsi/ufs/ufs-hisi.c
> index 452e19f8fb47..f2d3df357a97 100644
> --- a/drivers/scsi/ufs/ufs-hisi.c
> +++ b/drivers/scsi/ufs/ufs-hisi.c
> @@ -66,7 +66,7 @@ static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
> return err;
> }
>
> -static void ufs_hi3660_clk_init(struct ufs_hba *hba)
> +static void ufs_hisi_clk_init(struct ufs_hba *hba)
> {
> struct ufs_hisi_host *host = ufshcd_get_variant(hba);
>
> @@ -80,7 +80,7 @@ static void ufs_hi3660_clk_init(struct ufs_hba *hba)
> ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
> }
>
> -static void ufs_hi3660_soc_init(struct ufs_hba *hba)
> +static void ufs_hisi_soc_init(struct ufs_hba *hba)
> {
> struct ufs_hisi_host *host = ufshcd_get_variant(hba);
> u32 reg;
> @@ -139,6 +139,7 @@ static void ufs_hi3660_soc_init(struct ufs_hba *hba)
>
> static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
> {
> + struct ufs_hisi_host *host = ufshcd_get_variant(hba);
> int err;
> uint32_t value;
> uint32_t reg;
> @@ -153,6 +154,14 @@ static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
> ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D);
> /* MPHY CBOVRCTRL3 */
> ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1);
> +
> + if (host->caps & UFS_HISI_CAP_PHY10nm) {
> + /* MPHY CBOVRCTRL4 */
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8127, 0x0), 0x98);
> + /* MPHY CBOVRCTRL5 */
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8128, 0x0), 0x1);
> + }
> +
> /* Unipro VS_MphyCfgUpdt */
> ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
> /* MPHY RXOVRCTRL4 rx0 */
> @@ -173,10 +182,21 @@ static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
> ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8113, 0x0), 0x1);
> ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
>
> - /* Tactive RX */
> - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7);
> - /* Tactive RX */
> - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7);
> + if (host->caps & UFS_HISI_CAP_PHY10nm) {
> + /* RX_Hibern8Time_Capability*/
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x4), 0xA);
> + /* RX_Hibern8Time_Capability*/
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x5), 0xA);
> + /* RX_Min_ActivateTime */
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x4), 0xA);
> + /* RX_Min_ActivateTime*/
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x5), 0xA);
> + } else {
> + /* Tactive RX */
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7);
> + /* Tactive RX */
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7);
> + }
>
> /* Gear3 Synclength */
> ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x4), 0x4F);
> @@ -208,7 +228,8 @@ static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
> if (err)
> dev_err(hba->dev, "ufs_hisi_check_hibern8 error\n");
>
> - ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
> + if (!(host->caps & UFS_HISI_CAP_PHY10nm))
> + ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
>
> /* disable auto H8 */
> reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
> @@ -253,7 +274,7 @@ static int ufs_hisi_link_startup_post_change(struct ufs_hba *hba)
> return 0;
> }
>
> -static int ufs_hi3660_link_startup_notify(struct ufs_hba *hba,
> +static int ufs_hisi_link_startup_notify(struct ufs_hba *hba,
> enum ufs_notify_change_status status)
> {
> int err = 0;
> @@ -391,6 +412,28 @@ static void ufs_hisi_set_dev_cap(struct ufs_hisi_dev_params *hisi_param)
>
> static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
> {
> + struct ufs_hisi_host *host = ufshcd_get_variant(hba);
> +
> + if (host->caps & UFS_HISI_CAP_PHY10nm) {
> + /*
> + * Boston platform need to set SaveConfigTime to 0x13,
> + * and change sync length to maximum value
> + */
> + /* VS_DebugSaveConfigTime */
> + ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0xD0A0), 0x13);
> + /* g1 sync length */
> + ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1552), 0x4f);
> + /* g2 sync length */
> + ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1554), 0x4f);
> + /* g3 sync length */
> + ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1556), 0x4f);
> + /* PA_Hibern8Time */
> + ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a7), 0xA);
> + /* PA_Tactivate */
> + ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a8), 0xA);
> + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd085, 0x0), 0x01);
> + }
> +
> if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME) {
> pr_info("ufs flash device must set VS_DebugSaveConfigTime 0x10\n");
> /* VS_DebugSaveConfigTime */
> @@ -429,7 +472,7 @@ static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
> ufshcd_dme_set(hba, UIC_ARG_MIB(0xd046), 32767);
> }
>
> -static int ufs_hi3660_pwr_change_notify(struct ufs_hba *hba,
> +static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
> enum ufs_notify_change_status status,
> struct ufs_pa_layer_attr *dev_max_params,
> struct ufs_pa_layer_attr *dev_req_params)
> @@ -567,25 +610,72 @@ static int ufs_hi3660_init(struct ufs_hba *hba)
> return ret;
> }
>
> - ufs_hi3660_clk_init(hba);
> + ufs_hisi_clk_init(hba);
> +
> + ufs_hisi_soc_init(hba);
> +
> + return 0;
> +}
> +
> +static int ufs_hi3670_init(struct ufs_hba *hba)
> +{
> + int ret = 0;
> + struct device *dev = hba->dev;
> + struct ufs_hisi_host *host;
> +
> + ret = ufs_hisi_init_common(hba);
> + if (ret) {
> + dev_err(dev, "%s: ufs common init fail\n", __func__);
> + return ret;
> + }
> +
> + ufs_hisi_clk_init(hba);
> +
> + ufs_hisi_soc_init(hba);
>
> - ufs_hi3660_soc_init(hba);
> + /* Add cap for 10nm PHY variant on HI3670 SoC */
> + host = ufshcd_get_variant(hba);
> + host->caps |= UFS_HISI_CAP_PHY10nm;
>
> return 0;
> }
>
> -static struct ufs_hba_variant_ops ufs_hba_hisi_vops = {
> +static struct ufs_hba_variant_ops ufs_hba_hi3660_vops = {
> .name = "hi3660",
> .init = ufs_hi3660_init,
> - .link_startup_notify = ufs_hi3660_link_startup_notify,
> - .pwr_change_notify = ufs_hi3660_pwr_change_notify,
> + .link_startup_notify = ufs_hisi_link_startup_notify,
> + .pwr_change_notify = ufs_hisi_pwr_change_notify,
> .suspend = ufs_hisi_suspend,
> .resume = ufs_hisi_resume,
> };
>
> +static struct ufs_hba_variant_ops ufs_hba_hi3670_vops = {
> + .name = "hi3670",
> + .init = ufs_hi3670_init,
> + .link_startup_notify = ufs_hisi_link_startup_notify,
> + .pwr_change_notify = ufs_hisi_pwr_change_notify,
> + .suspend = ufs_hisi_suspend,
> + .resume = ufs_hisi_resume,
> +};
> +
> +static const struct of_device_id ufs_hisi_of_match[] = {
> + { .compatible = "hisilicon,hi3660-ufs", .data = &ufs_hba_hi3660_vops },
> + { .compatible = "hisilicon,hi3670-ufs", .data = &ufs_hba_hi3670_vops },
> + {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, ufs_hisi_of_match);
> +
> static int ufs_hisi_probe(struct platform_device *pdev)
> {
> - return ufshcd_pltfrm_init(pdev, &ufs_hba_hisi_vops);
> + const struct of_device_id *of_id;
> + struct ufs_hba_variant_ops *vops;
> + struct device *dev = &pdev->dev;
> +
> + of_id = of_match_node(ufs_hisi_of_match, dev->of_node);
> + vops = (struct ufs_hba_variant_ops *)of_id->data;
> +
> + return ufshcd_pltfrm_init(pdev, vops);
> }
>
> static int ufs_hisi_remove(struct platform_device *pdev)
> @@ -596,13 +686,6 @@ static int ufs_hisi_remove(struct platform_device *pdev)
> return 0;
> }
>
> -static const struct of_device_id ufs_hisi_of_match[] = {
> - { .compatible = "hisilicon,hi3660-ufs" },
> - {},
> -};
> -
> -MODULE_DEVICE_TABLE(of, ufs_hisi_of_match);
> -
> static const struct dev_pm_ops ufs_hisi_pm_ops = {
> .suspend = ufshcd_pltfrm_suspend,
> .resume = ufshcd_pltfrm_resume,
> diff --git a/drivers/scsi/ufs/ufs-hisi.h b/drivers/scsi/ufs/ufs-hisi.h
> index 3df9cd7acc29..667dfe39b57e 100644
> --- a/drivers/scsi/ufs/ufs-hisi.h
> +++ b/drivers/scsi/ufs/ufs-hisi.h
> @@ -91,6 +91,9 @@ enum {
> #define UFS_HISI_LIMIT_HS_RATE PA_HS_MODE_B
> #define UFS_HISI_LIMIT_DESIRED_MODE FAST
>
> +#define UFS_HISI_CAP_RESERVED BIT(0)
> +#define UFS_HISI_CAP_PHY10nm BIT(1)
> +
> struct ufs_hisi_host {
> struct ufs_hba *hba;
> void __iomem *ufs_sys_ctrl;
> @@ -112,4 +115,5 @@ struct ufs_hisi_host {
> ufs_sys_ctrl_writel((host), \
> ((~(mask)) & (ufs_sys_ctrl_readl((host), (reg)))), \
> (reg))
> +
> #endif /* UFS_HISI_H_ */
> --
> 2.17.1
>
Manivannan,
> Ping on this patch!
I don't have any objections except I would like to see an Acked-by: from
Wei Li or somebody from hisilicon.
--
Martin K. Petersen Oracle Linux Engineering
Fine to me. Thanks!
Acked-by: Wei Li <[email protected]>
-----?ʼ?ԭ??-----
??????: Manivannan Sadhasivam [mailto:[email protected]]
????ʱ??: 2019??1??5?? 15:29
?ռ???: [email protected]; [email protected]; [email protected]; liwei (CM); [email protected]
????: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Manivannan Sadhasivam
????: [PATCH v2 1/3] dt-bindings: ufs: Add HI3670 UFS controller binding
Add devicetree binding for HI3670 UFS controller. HI3760 SoC is very
similar to HI3660 SoC with almost same IPs. Only major difference in terms
of UFS is the PHY. HI3670 has 10nm PHY. But since the original driver
(HI3660 UFS) cannot make HI3670 UFS functional, a separate compatible
is added for HI3670 without any fallback.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt
index a48c44817367..0b83df1a5418 100644
--- a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt
+++ b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt
@@ -6,9 +6,10 @@ Each UFS Host Controller should have its own node.
Required properties:
- compatible : compatible list, contains one of the following -
"hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs
- host controller present on Hi36xx chipset.
+ host controller present on Hi3660 chipset.
+ "hisilicon,hi3670-ufs", "jedec,ufs-2.1" for hisi ufs
+ host controller present on Hi3670 chipset.
- reg : should contain UFS register address space & UFS SYS CTRL register address,
-- interrupt-parent : interrupt device
- interrupts : interrupt number
- clocks : List of phandle and clock specifier pairs
- clock-names : List of clock input name strings sorted in the same
--
2.17.1
Fine to me. Thanks!
Acked-by: Wei Li <[email protected]>
-----?ʼ?ԭ??-----
??????: Manivannan Sadhasivam [mailto:[email protected]]
????ʱ??: 2019??1??5?? 15:29
?ռ???: [email protected]; [email protected]; [email protected]; liwei (CM); [email protected]
????: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Manivannan Sadhasivam
????: [PATCH v2 3/3] scsi: ufs: Add HI3670 SoC UFS driver support
Add HI3670 SoC UFS driver support by extending the common ufs-hisi
driver. One major difference between HI3660 ad HI3670 SoCs interms of
UFS is the PHY. HI3670 has a 10nm variant PHY and hence this parameter is
used to distinguish the configuration.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/scsi/ufs/ufs-hisi.c | 127 +++++++++++++++++++++++++++++-------
drivers/scsi/ufs/ufs-hisi.h | 4 ++
2 files changed, 109 insertions(+), 22 deletions(-)
diff --git a/drivers/scsi/ufs/ufs-hisi.c b/drivers/scsi/ufs/ufs-hisi.c
index 452e19f8fb47..f2d3df357a97 100644
--- a/drivers/scsi/ufs/ufs-hisi.c
+++ b/drivers/scsi/ufs/ufs-hisi.c
@@ -66,7 +66,7 @@ static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
return err;
}
-static void ufs_hi3660_clk_init(struct ufs_hba *hba)
+static void ufs_hisi_clk_init(struct ufs_hba *hba)
{
struct ufs_hisi_host *host = ufshcd_get_variant(hba);
@@ -80,7 +80,7 @@ static void ufs_hi3660_clk_init(struct ufs_hba *hba)
ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
}
-static void ufs_hi3660_soc_init(struct ufs_hba *hba)
+static void ufs_hisi_soc_init(struct ufs_hba *hba)
{
struct ufs_hisi_host *host = ufshcd_get_variant(hba);
u32 reg;
@@ -139,6 +139,7 @@ static void ufs_hi3660_soc_init(struct ufs_hba *hba)
static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
{
+ struct ufs_hisi_host *host = ufshcd_get_variant(hba);
int err;
uint32_t value;
uint32_t reg;
@@ -153,6 +154,14 @@ static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D);
/* MPHY CBOVRCTRL3 */
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1);
+
+ if (host->caps & UFS_HISI_CAP_PHY10nm) {
+ /* MPHY CBOVRCTRL4 */
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8127, 0x0), 0x98);
+ /* MPHY CBOVRCTRL5 */
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8128, 0x0), 0x1);
+ }
+
/* Unipro VS_MphyCfgUpdt */
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
/* MPHY RXOVRCTRL4 rx0 */
@@ -173,10 +182,21 @@ static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8113, 0x0), 0x1);
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
- /* Tactive RX */
- ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7);
- /* Tactive RX */
- ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7);
+ if (host->caps & UFS_HISI_CAP_PHY10nm) {
+ /* RX_Hibern8Time_Capability*/
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x4), 0xA);
+ /* RX_Hibern8Time_Capability*/
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x5), 0xA);
+ /* RX_Min_ActivateTime */
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x4), 0xA);
+ /* RX_Min_ActivateTime*/
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x5), 0xA);
+ } else {
+ /* Tactive RX */
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7);
+ /* Tactive RX */
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7);
+ }
/* Gear3 Synclength */
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x4), 0x4F);
@@ -208,7 +228,8 @@ static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
if (err)
dev_err(hba->dev, "ufs_hisi_check_hibern8 error\n");
- ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
+ if (!(host->caps & UFS_HISI_CAP_PHY10nm))
+ ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
/* disable auto H8 */
reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
@@ -253,7 +274,7 @@ static int ufs_hisi_link_startup_post_change(struct ufs_hba *hba)
return 0;
}
-static int ufs_hi3660_link_startup_notify(struct ufs_hba *hba,
+static int ufs_hisi_link_startup_notify(struct ufs_hba *hba,
enum ufs_notify_change_status status)
{
int err = 0;
@@ -391,6 +412,28 @@ static void ufs_hisi_set_dev_cap(struct ufs_hisi_dev_params *hisi_param)
static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
{
+ struct ufs_hisi_host *host = ufshcd_get_variant(hba);
+
+ if (host->caps & UFS_HISI_CAP_PHY10nm) {
+ /*
+ * Boston platform need to set SaveConfigTime to 0x13,
+ * and change sync length to maximum value
+ */
+ /* VS_DebugSaveConfigTime */
+ ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0xD0A0), 0x13);
+ /* g1 sync length */
+ ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1552), 0x4f);
+ /* g2 sync length */
+ ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1554), 0x4f);
+ /* g3 sync length */
+ ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x1556), 0x4f);
+ /* PA_Hibern8Time */
+ ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a7), 0xA);
+ /* PA_Tactivate */
+ ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a8), 0xA);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd085, 0x0), 0x01);
+ }
+
if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME) {
pr_info("ufs flash device must set VS_DebugSaveConfigTime 0x10\n");
/* VS_DebugSaveConfigTime */
@@ -429,7 +472,7 @@ static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
ufshcd_dme_set(hba, UIC_ARG_MIB(0xd046), 32767);
}
-static int ufs_hi3660_pwr_change_notify(struct ufs_hba *hba,
+static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
enum ufs_notify_change_status status,
struct ufs_pa_layer_attr *dev_max_params,
struct ufs_pa_layer_attr *dev_req_params)
@@ -567,25 +610,72 @@ static int ufs_hi3660_init(struct ufs_hba *hba)
return ret;
}
- ufs_hi3660_clk_init(hba);
+ ufs_hisi_clk_init(hba);
+
+ ufs_hisi_soc_init(hba);
+
+ return 0;
+}
+
+static int ufs_hi3670_init(struct ufs_hba *hba)
+{
+ int ret = 0;
+ struct device *dev = hba->dev;
+ struct ufs_hisi_host *host;
+
+ ret = ufs_hisi_init_common(hba);
+ if (ret) {
+ dev_err(dev, "%s: ufs common init fail\n", __func__);
+ return ret;
+ }
+
+ ufs_hisi_clk_init(hba);
+
+ ufs_hisi_soc_init(hba);
- ufs_hi3660_soc_init(hba);
+ /* Add cap for 10nm PHY variant on HI3670 SoC */
+ host = ufshcd_get_variant(hba);
+ host->caps |= UFS_HISI_CAP_PHY10nm;
return 0;
}
-static struct ufs_hba_variant_ops ufs_hba_hisi_vops = {
+static struct ufs_hba_variant_ops ufs_hba_hi3660_vops = {
.name = "hi3660",
.init = ufs_hi3660_init,
- .link_startup_notify = ufs_hi3660_link_startup_notify,
- .pwr_change_notify = ufs_hi3660_pwr_change_notify,
+ .link_startup_notify = ufs_hisi_link_startup_notify,
+ .pwr_change_notify = ufs_hisi_pwr_change_notify,
.suspend = ufs_hisi_suspend,
.resume = ufs_hisi_resume,
};
+static struct ufs_hba_variant_ops ufs_hba_hi3670_vops = {
+ .name = "hi3670",
+ .init = ufs_hi3670_init,
+ .link_startup_notify = ufs_hisi_link_startup_notify,
+ .pwr_change_notify = ufs_hisi_pwr_change_notify,
+ .suspend = ufs_hisi_suspend,
+ .resume = ufs_hisi_resume,
+};
+
+static const struct of_device_id ufs_hisi_of_match[] = {
+ { .compatible = "hisilicon,hi3660-ufs", .data = &ufs_hba_hi3660_vops },
+ { .compatible = "hisilicon,hi3670-ufs", .data = &ufs_hba_hi3670_vops },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, ufs_hisi_of_match);
+
static int ufs_hisi_probe(struct platform_device *pdev)
{
- return ufshcd_pltfrm_init(pdev, &ufs_hba_hisi_vops);
+ const struct of_device_id *of_id;
+ struct ufs_hba_variant_ops *vops;
+ struct device *dev = &pdev->dev;
+
+ of_id = of_match_node(ufs_hisi_of_match, dev->of_node);
+ vops = (struct ufs_hba_variant_ops *)of_id->data;
+
+ return ufshcd_pltfrm_init(pdev, vops);
}
static int ufs_hisi_remove(struct platform_device *pdev)
@@ -596,13 +686,6 @@ static int ufs_hisi_remove(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id ufs_hisi_of_match[] = {
- { .compatible = "hisilicon,hi3660-ufs" },
- {},
-};
-
-MODULE_DEVICE_TABLE(of, ufs_hisi_of_match);
-
static const struct dev_pm_ops ufs_hisi_pm_ops = {
.suspend = ufshcd_pltfrm_suspend,
.resume = ufshcd_pltfrm_resume,
diff --git a/drivers/scsi/ufs/ufs-hisi.h b/drivers/scsi/ufs/ufs-hisi.h
index 3df9cd7acc29..667dfe39b57e 100644
--- a/drivers/scsi/ufs/ufs-hisi.h
+++ b/drivers/scsi/ufs/ufs-hisi.h
@@ -91,6 +91,9 @@ enum {
#define UFS_HISI_LIMIT_HS_RATE PA_HS_MODE_B
#define UFS_HISI_LIMIT_DESIRED_MODE FAST
+#define UFS_HISI_CAP_RESERVED BIT(0)
+#define UFS_HISI_CAP_PHY10nm BIT(1)
+
struct ufs_hisi_host {
struct ufs_hba *hba;
void __iomem *ufs_sys_ctrl;
@@ -112,4 +115,5 @@ struct ufs_hisi_host {
ufs_sys_ctrl_writel((host), \
((~(mask)) & (ufs_sys_ctrl_readl((host), (reg)))), \
(reg))
+
#endif /* UFS_HISI_H_ */
--
2.17.1
Fine to me. Thanks!
Acked-by: Wei Li <[email protected]>
-----?ʼ?ԭ??-----
??????: Manivannan Sadhasivam [mailto:[email protected]]
????ʱ??: 2019??1??5?? 15:29
?ռ???: [email protected]; [email protected]; [email protected]; liwei (CM); [email protected]
????: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Manivannan Sadhasivam
????: [PATCH v2 2/3] arm64: dts: hisilicon: hi3670: Add UFS controller support
Add UFS controller support for HiSilicon HI3670 SoC.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 6ccdf5040ffd..285219dd657f 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -654,6 +654,24 @@
clock-names = "apb_pclk";
};
+ /* UFS */
+ ufs: ufs@ff3c0000 {
+ compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
+ /* 0: HCI standard */
+ /* 1: UFS SYS CTRL */
+ reg = <0x0 0xff3c0000 0x0 0x1000>,
+ <0x0 0xff3e0000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
+ <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
+ clock-names = "ref_clk", "phy_clk";
+ freq-table-hz = <0 0>, <0 0>;
+ /* offset: 0x84; bit: 12 */
+ resets = <&crg_rst 0x84 12>;
+ reset-names = "rst";
+ };
+
/* SD */
dwmmc1: dwmmc1@ff37f000 {
compatible = "hisilicon,hi3670-dw-mshc";
--
2.17.1
Manivannan,
> Ping on this patch!
Applied to 5.1/scsi-queue, thanks!
--
Martin K. Petersen Oracle Linux Engineering
On Fri, Jan 11, 2019 at 03:35:02PM -0600, Rob Herring wrote:
> On Sat, 5 Jan 2019 12:58:57 +0530, Manivannan Sadhasivam wrote:
> > Add devicetree binding for HI3670 UFS controller. HI3760 SoC is very
> > similar to HI3660 SoC with almost same IPs. Only major difference in terms
> > of UFS is the PHY. HI3670 has 10nm PHY. But since the original driver
> > (HI3660 UFS) cannot make HI3670 UFS functional, a separate compatible
> > is added for HI3670 without any fallback.
> >
> > Signed-off-by: Manivannan Sadhasivam <[email protected]>
> > ---
> > Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
>
> Reviewed-by: Rob Herring <[email protected]>
Martin,
Can you please take the bindings patch also? DT patch will go through
HiSi tree.
Thanks,
Mani
On Sat, Jan 05, 2019 at 12:58:58PM +0530, Manivannan Sadhasivam wrote:
> Add UFS controller support for HiSilicon HI3670 SoC.
>
> Signed-off-by: Manivannan Sadhasivam <[email protected]>
> ---
> arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
Hi Martin,
it looks like you picked this up into the SCSI tree (perhaps
inadvertently). It's been causing linux-next to fail to build since
Monday (next-20190218) because it references a phandle (&crg_rst)
that's not available.
There's a patch on the mailing lists to add that, but I think at this
point it'd be better if you could drop this from the SCSI tree and we
let the HiSilicon maintainers deal with the dependency in their tree.
Cc'ing Wei and linux-next.
Thierry
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> index 6ccdf5040ffd..285219dd657f 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> @@ -654,6 +654,24 @@
> clock-names = "apb_pclk";
> };
>
> + /* UFS */
> + ufs: ufs@ff3c0000 {
> + compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
> + /* 0: HCI standard */
> + /* 1: UFS SYS CTRL */
> + reg = <0x0 0xff3c0000 0x0 0x1000>,
> + <0x0 0xff3e0000 0x0 0x1000>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
> + <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
> + clock-names = "ref_clk", "phy_clk";
> + freq-table-hz = <0 0>, <0 0>;
> + /* offset: 0x84; bit: 12 */
> + resets = <&crg_rst 0x84 12>;
> + reset-names = "rst";
> + };
> +
> /* SD */
> dwmmc1: dwmmc1@ff37f000 {
> compatible = "hisilicon,hi3670-dw-mshc";
> --
> 2.17.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Thierry,
> it looks like you picked this up into the SCSI tree (perhaps
> inadvertently). It's been causing linux-next to fail to build since
> Monday (next-20190218) because it references a phandle (&crg_rst)
> that's not available.
I dropped the offending patch from the SCSI tree yesterday. When Stephen
updates -next, things should be fine.
--
Martin K. Petersen Oracle Linux Engineering
Hi Manivannan,
On 2/20/2019 2:21 PM, Martin K. Petersen wrote:
>
> Hi Thierry,
>
>> it looks like you picked this up into the SCSI tree (perhaps
>> inadvertently). It's been causing linux-next to fail to build since
>> Monday (next-20190218) because it references a phandle (&crg_rst)
>> that's not available.
>
> I dropped the offending patch from the SCSI tree yesterday. When Stephen
> updates -next, things should be fine.
>
Thanks!
Applied the dts patch to the hisilicon dts tree.
Best Regards,
Wei