Add support for PWM on the MediaTek MT7981 to pwm-mediatek.c as well
as new mediatek,mt7981-pwm compatible string to the existing bindings.
Changes since v2:
* improve commit message, adding that alphabetic order is restored
Changes since v1:
* use pointer to reg_offset instead of u8 reg_ver and if-else
Daniel Golle (2):
dt-bindings: pwm: mediatek: Add mediatek,mt7981 compatible
pwm: mediatek: Add support for MT7981
.../bindings/pwm/mediatek,mt2712-pwm.yaml | 1 +
drivers/pwm/pwm-mediatek.c | 39 +++++++++++++++----
2 files changed, 32 insertions(+), 8 deletions(-)
base-commit: 44bf136283e567b2b62653be7630e7511da41da2
--
2.40.0
Add compatible string for the PWM unit found of the MediaTek MT7981 SoC.
This is in preparation to adding support in the pwm-mediatek.c driver.
Signed-off-by: Daniel Golle <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml b/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml
index 8e176ba7a525f..0fbe8a6469eb2 100644
--- a/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml
@@ -22,6 +22,7 @@ properties:
- mediatek,mt7623-pwm
- mediatek,mt7628-pwm
- mediatek,mt7629-pwm
+ - mediatek,mt7981-pwm
- mediatek,mt7986-pwm
- mediatek,mt8183-pwm
- mediatek,mt8365-pwm
--
2.40.0
The PWM unit on MT7981 uses different register offsets than previous
MediaTek PWM units. Add support for these new offsets and add support
for PWM on MT7981 which has 3 PWM channels, one of them is typically
used for a temperature controlled fan.
While at it, also reorder pwm_mediatek_of_data entries to restore
alphabetic order.
Signed-off-by: Daniel Golle <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
---
drivers/pwm/pwm-mediatek.c | 39 ++++++++++++++++++++++++++++++--------
1 file changed, 31 insertions(+), 8 deletions(-)
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index 5b5eeaff35da6..7a51d210a8778 100644
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -38,6 +38,7 @@ struct pwm_mediatek_of_data {
unsigned int num_pwms;
bool pwm45_fixup;
bool has_ck_26m_sel;
+ const unsigned int *reg_offset;
};
/**
@@ -59,10 +60,14 @@ struct pwm_mediatek_chip {
const struct pwm_mediatek_of_data *soc;
};
-static const unsigned int pwm_mediatek_reg_offset[] = {
+static const unsigned int mtk_pwm_reg_offset_v1[] = {
0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
};
+static const unsigned int mtk_pwm_reg_offset_v2[] = {
+ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
+};
+
static inline struct pwm_mediatek_chip *
to_pwm_mediatek_chip(struct pwm_chip *chip)
{
@@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
unsigned int num, unsigned int offset,
u32 value)
{
- writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
+ writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
}
static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
@@ -285,60 +290,77 @@ static const struct pwm_mediatek_of_data mt2712_pwm_data = {
.num_pwms = 8,
.pwm45_fixup = false,
.has_ck_26m_sel = false,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
static const struct pwm_mediatek_of_data mt6795_pwm_data = {
.num_pwms = 7,
.pwm45_fixup = false,
.has_ck_26m_sel = false,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
static const struct pwm_mediatek_of_data mt7622_pwm_data = {
.num_pwms = 6,
.pwm45_fixup = false,
.has_ck_26m_sel = true,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
static const struct pwm_mediatek_of_data mt7623_pwm_data = {
.num_pwms = 5,
.pwm45_fixup = true,
.has_ck_26m_sel = false,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
static const struct pwm_mediatek_of_data mt7628_pwm_data = {
.num_pwms = 4,
.pwm45_fixup = true,
.has_ck_26m_sel = false,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
static const struct pwm_mediatek_of_data mt7629_pwm_data = {
.num_pwms = 1,
.pwm45_fixup = false,
.has_ck_26m_sel = false,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
-static const struct pwm_mediatek_of_data mt8183_pwm_data = {
- .num_pwms = 4,
+static const struct pwm_mediatek_of_data mt7981_pwm_data = {
+ .num_pwms = 3,
.pwm45_fixup = false,
.has_ck_26m_sel = true,
+ .reg_offset = mtk_pwm_reg_offset_v2,
};
-static const struct pwm_mediatek_of_data mt8365_pwm_data = {
- .num_pwms = 3,
+static const struct pwm_mediatek_of_data mt7986_pwm_data = {
+ .num_pwms = 2,
.pwm45_fixup = false,
.has_ck_26m_sel = true,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
-static const struct pwm_mediatek_of_data mt7986_pwm_data = {
- .num_pwms = 2,
+static const struct pwm_mediatek_of_data mt8183_pwm_data = {
+ .num_pwms = 4,
+ .pwm45_fixup = false,
+ .has_ck_26m_sel = true,
+ .reg_offset = mtk_pwm_reg_offset_v1,
+};
+
+static const struct pwm_mediatek_of_data mt8365_pwm_data = {
+ .num_pwms = 3,
.pwm45_fixup = false,
.has_ck_26m_sel = true,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
static const struct pwm_mediatek_of_data mt8516_pwm_data = {
.num_pwms = 5,
.pwm45_fixup = false,
.has_ck_26m_sel = true,
+ .reg_offset = mtk_pwm_reg_offset_v1,
};
static const struct of_device_id pwm_mediatek_of_match[] = {
@@ -348,6 +370,7 @@ static const struct of_device_id pwm_mediatek_of_match[] = {
{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
+ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
{ .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
--
2.40.0
On 21/04/2023 01:23, Daniel Golle wrote:
> The PWM unit on MT7981 uses different register offsets than previous
> MediaTek PWM units. Add support for these new offsets and add support
> for PWM on MT7981 which has 3 PWM channels, one of them is typically
> used for a temperature controlled fan.
> While at it, also reorder pwm_mediatek_of_data entries to restore
> alphabetic order.
>
> Signed-off-by: Daniel Golle <[email protected]>
> Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
> ---
> drivers/pwm/pwm-mediatek.c | 39 ++++++++++++++++++++++++++++++--------
> 1 file changed, 31 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
> index 5b5eeaff35da6..7a51d210a8778 100644
> --- a/drivers/pwm/pwm-mediatek.c
> +++ b/drivers/pwm/pwm-mediatek.c
> @@ -38,6 +38,7 @@ struct pwm_mediatek_of_data {
> unsigned int num_pwms;
> bool pwm45_fixup;
> bool has_ck_26m_sel;
> + const unsigned int *reg_offset;
> };
>
> /**
> @@ -59,10 +60,14 @@ struct pwm_mediatek_chip {
> const struct pwm_mediatek_of_data *soc;
> };
>
> -static const unsigned int pwm_mediatek_reg_offset[] = {
> +static const unsigned int mtk_pwm_reg_offset_v1[] = {
> 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
> };
>
> +static const unsigned int mtk_pwm_reg_offset_v2[] = {
> + 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
> +};
> +
> static inline struct pwm_mediatek_chip *
> to_pwm_mediatek_chip(struct pwm_chip *chip)
> {
> @@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip,
> unsigned int num, unsigned int offset,
> u32 value)
> {
> - writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
> + writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
> }
>
> static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
> @@ -285,60 +290,77 @@ static const struct pwm_mediatek_of_data mt2712_pwm_data = {
> .num_pwms = 8,
> .pwm45_fixup = false,
> .has_ck_26m_sel = false,
> + .reg_offset = mtk_pwm_reg_offset_v1,
> };
>
> static const struct pwm_mediatek_of_data mt6795_pwm_data = {
> .num_pwms = 7,
> .pwm45_fixup = false,
> .has_ck_26m_sel = false,
> + .reg_offset = mtk_pwm_reg_offset_v1,
> };
>
> static const struct pwm_mediatek_of_data mt7622_pwm_data = {
> .num_pwms = 6,
> .pwm45_fixup = false,
> .has_ck_26m_sel = true,
> + .reg_offset = mtk_pwm_reg_offset_v1,
> };
>
> static const struct pwm_mediatek_of_data mt7623_pwm_data = {
> .num_pwms = 5,
> .pwm45_fixup = true,
> .has_ck_26m_sel = false,
> + .reg_offset = mtk_pwm_reg_offset_v1,
> };
>
> static const struct pwm_mediatek_of_data mt7628_pwm_data = {
> .num_pwms = 4,
> .pwm45_fixup = true,
> .has_ck_26m_sel = false,
> + .reg_offset = mtk_pwm_reg_offset_v1,
> };
>
> static const struct pwm_mediatek_of_data mt7629_pwm_data = {
> .num_pwms = 1,
> .pwm45_fixup = false,
> .has_ck_26m_sel = false,
> + .reg_offset = mtk_pwm_reg_offset_v1,
> };
>
> -static const struct pwm_mediatek_of_data mt8183_pwm_data = {
> - .num_pwms = 4,
> +static const struct pwm_mediatek_of_data mt7981_pwm_data = {
> + .num_pwms = 3,
> .pwm45_fixup = false,
> .has_ck_26m_sel = true,
> + .reg_offset = mtk_pwm_reg_offset_v2,
> };
>
> -static const struct pwm_mediatek_of_data mt8365_pwm_data = {
> - .num_pwms = 3,
> +static const struct pwm_mediatek_of_data mt7986_pwm_data = {
> + .num_pwms = 2,
> .pwm45_fixup = false,
> .has_ck_26m_sel = true,
> + .reg_offset = mtk_pwm_reg_offset_v1,
> };
>
> -static const struct pwm_mediatek_of_data mt7986_pwm_data = {
> - .num_pwms = 2,
> +static const struct pwm_mediatek_of_data mt8183_pwm_data = {
> + .num_pwms = 4,
> + .pwm45_fixup = false,
> + .has_ck_26m_sel = true,
> + .reg_offset = mtk_pwm_reg_offset_v1,
> +};
> +
> +static const struct pwm_mediatek_of_data mt8365_pwm_data = {
> + .num_pwms = 3,
> .pwm45_fixup = false,
> .has_ck_26m_sel = true,
> + .reg_offset = mtk_pwm_reg_offset_v1,
> };
>
> static const struct pwm_mediatek_of_data mt8516_pwm_data = {
> .num_pwms = 5,
> .pwm45_fixup = false,
> .has_ck_26m_sel = true,
> + .reg_offset = mtk_pwm_reg_offset_v1,
> };
>
> static const struct of_device_id pwm_mediatek_of_match[] = {
> @@ -348,6 +370,7 @@ static const struct of_device_id pwm_mediatek_of_match[] = {
> { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
> { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
> { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
> + { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
> { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
> { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
> { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
Hello,
On Fri, Apr 21, 2023 at 12:22:20AM +0100, Daniel Golle wrote:
> Add support for PWM on the MediaTek MT7981 to pwm-mediatek.c as well
> as new mediatek,mt7981-pwm compatible string to the existing bindings.
>
> Changes since v2:
> * improve commit message, adding that alphabetic order is restored
>
> Changes since v1:
> * use pointer to reg_offset instead of u8 reg_ver and if-else
>
> Daniel Golle (2):
> dt-bindings: pwm: mediatek: Add mediatek,mt7981 compatible
> pwm: mediatek: Add support for MT7981
>
> .../bindings/pwm/mediatek,mt2712-pwm.yaml | 1 +
> drivers/pwm/pwm-mediatek.c | 39 +++++++++++++++----
> 2 files changed, 32 insertions(+), 8 deletions(-)
whole series looks good to me,
Acked-by: Uwe Kleine-K?nig <[email protected]>
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
On Fri, 21 Apr 2023 00:22:20 +0100, Daniel Golle wrote:
> Add support for PWM on the MediaTek MT7981 to pwm-mediatek.c as well
> as new mediatek,mt7981-pwm compatible string to the existing bindings.
>
> Changes since v2:
> * improve commit message, adding that alphabetic order is restored
>
> Changes since v1:
> * use pointer to reg_offset instead of u8 reg_ver and if-else
>
> [...]
Applied, thanks!
[1/2] dt-bindings: pwm: mediatek: Add mediatek,mt7981 compatible
commit: 88c66e018aa8b5a15d7fdba9908c01260c657bff
[2/2] pwm: mediatek: Add support for MT7981
commit: 967da67a745fb73fd0fc7aa61fd197b76fceb273
Best regards,
--
Thierry Reding <[email protected]>