In a multiprocessor system cache snooping maintains the consistency
of caches. Snooping logic is disabled from HW on this platform.
Cache coherency doesn’t work without enabling this logic.
This series is to enable cache snooping logic in both RC and EP
driver and add the "dma-coherent" property in dtsi to support
cache coherency in 8775 platform.
To verify this series we required [1]
[1] https://lore.kernel.org/all/[email protected]/
v2 -> v3:
- update commit message(8755 -> 8775).
v1 -> v2:
- update cover letter with explanation.
- define each of these bits and ORing at usage time rather than
directly writing value in register.
Mrinmay Sarkar (3):
PCI: qcom: Enable cache coherency for SA8775P RC
PCI: qcom-ep: Enable cache coherency for SA8775P EP
arm64: dts: qcom: sa8775p: Mark PCIe controller as cache coherent
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 +
drivers/pci/controller/dwc/pcie-qcom-ep.c | 10 ++++++++++
drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
3 files changed, 24 insertions(+)
--
2.7.4
The PCIe controller on SA8775P supports cache coherency, hence add the
"dma-coherent" property to mark it as such.
Signed-off-by: Mrinmay Sarkar <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 7eab458..ab01efe 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3620,6 +3620,7 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
+ dma-coherent;
iommus = <&pcie_smmu 0x0000 0x7f>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "core";
--
2.7.4
This change will enable cache snooping logic to support
cache coherency for 8775 EP platform.
Signed-off-by: Mrinmay Sarkar <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom-ep.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 3a53d97..ee99fb1 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -47,6 +47,7 @@
#define PARF_DBI_BASE_ADDR_HI 0x354
#define PARF_SLV_ADDR_SPACE_SIZE 0x358
#define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c
+#define PCIE_PARF_NO_SNOOP_OVERIDE 0x3d4
#define PARF_ATU_BASE_ADDR 0x634
#define PARF_ATU_BASE_ADDR_HI 0x638
#define PARF_SRIS_MODE 0x644
@@ -86,6 +87,10 @@
#define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2)
#define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3)
+/* PARF_NO_SNOOP_OVERIDE register fields */
+#define WR_NO_SNOOP_OVERIDE_EN BIT(1)
+#define RD_NO_SNOOP_OVERIDE_EN BIT(3)
+
/* PARF_DEVICE_TYPE register fields */
#define PARF_DEVICE_TYPE_EP 0x0
@@ -489,6 +494,11 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
val |= BIT(8);
writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
+ /* Enable cache snooping for SA8775P */
+ if (of_device_is_compatible(dev->of_node, "qcom,sa8775p-pcie-ep"))
+ writel_relaxed(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN,
+ pcie_ep->parf + PCIE_PARF_NO_SNOOP_OVERIDE);
+
return 0;
err_disable_resources:
--
2.7.4
On Wed, Nov 15, 2023 at 06:07:00PM +0530, Mrinmay Sarkar wrote:
> This change will enable cache snooping logic to support
> cache coherency for 8775 EP platform.
>
> Signed-off-by: Mrinmay Sarkar <[email protected]>
Same comment as patch 1/3.
- Mani
> ---
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index 3a53d97..ee99fb1 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -47,6 +47,7 @@
> #define PARF_DBI_BASE_ADDR_HI 0x354
> #define PARF_SLV_ADDR_SPACE_SIZE 0x358
> #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c
> +#define PCIE_PARF_NO_SNOOP_OVERIDE 0x3d4
> #define PARF_ATU_BASE_ADDR 0x634
> #define PARF_ATU_BASE_ADDR_HI 0x638
> #define PARF_SRIS_MODE 0x644
> @@ -86,6 +87,10 @@
> #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2)
> #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3)
>
> +/* PARF_NO_SNOOP_OVERIDE register fields */
> +#define WR_NO_SNOOP_OVERIDE_EN BIT(1)
> +#define RD_NO_SNOOP_OVERIDE_EN BIT(3)
> +
> /* PARF_DEVICE_TYPE register fields */
> #define PARF_DEVICE_TYPE_EP 0x0
>
> @@ -489,6 +494,11 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
> val |= BIT(8);
> writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
>
> + /* Enable cache snooping for SA8775P */
> + if (of_device_is_compatible(dev->of_node, "qcom,sa8775p-pcie-ep"))
> + writel_relaxed(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN,
> + pcie_ep->parf + PCIE_PARF_NO_SNOOP_OVERIDE);
> +
> return 0;
>
> err_disable_resources:
> --
> 2.7.4
>
--
மணிவண்ணன் சதாசிவம்
On Wed, Nov 15, 2023 at 06:07:01PM +0530, Mrinmay Sarkar wrote:
> The PCIe controller on SA8775P supports cache coherency, hence add the
"PCIe RC controller" both in subject and description.
> "dma-coherent" property to mark it as such.
>
> Signed-off-by: Mrinmay Sarkar <[email protected]>
With that,
Reviewed-by: Manivannan Sadhasivam <[email protected]>
- Mani
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 7eab458..ab01efe 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -3620,6 +3620,7 @@
> <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
> interconnect-names = "pcie-mem", "cpu-pcie";
>
> + dma-coherent;
> iommus = <&pcie_smmu 0x0000 0x7f>;
> resets = <&gcc GCC_PCIE_0_BCR>;
> reset-names = "core";
> --
> 2.7.4
>
--
மணிவண்ணன் சதாசிவம்
On 11/17/2023 2:36 PM, Manivannan Sadhasivam wrote:
> On Wed, Nov 15, 2023 at 06:07:01PM +0530, Mrinmay Sarkar wrote:
>> The PCIe controller on SA8775P supports cache coherency, hence add the
> "PCIe RC controller" both in subject and description.
This is for EP so will make as "PCIe EP controller"
--Mrinmay
>> "dma-coherent" property to mark it as such.
>>
>> Signed-off-by: Mrinmay Sarkar <[email protected]>
> With that,
>
> Reviewed-by: Manivannan Sadhasivam <[email protected]>
>
> - Mani
>
>> ---
>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> index 7eab458..ab01efe 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> @@ -3620,6 +3620,7 @@
>> <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
>> interconnect-names = "pcie-mem", "cpu-pcie";
>>
>> + dma-coherent;
>> iommus = <&pcie_smmu 0x0000 0x7f>;
>> resets = <&gcc GCC_PCIE_0_BCR>;
>> reset-names = "core";
>> --
>> 2.7.4
>>