While interestingly the DT-binding for the Innosilicon usb phy found in
RK3128 SoC exists already and it is exposed in the SoC DT, it has never
been added to the driver.
This patch-set adds support for this early version of the phy and does
some DT-fixups in order to make the 2-port host/otg phy and the respective
controllers work.
Please see commit messages of the individual patches for details.
Changes in v3:
- rebased on linux-next
- added phy-tuning callback for RK3128
- moved parent clock assignment of SCLK_USB480M to the phy node
Alex Bee (5):
phy: rockchip-inno-usb2: Split ID interrupt phy registers
phy: phy-rockchip-inno-usb2: Add RK3128 support
ARM: dts: rockchip: Add USB host clocks for RK3128
ARM: dts: rockchip: Add dwc2 otg fifo siztes for RK3128
ARM: dts: rockchip: Make usbphy the parent of SCLK_USB480M for RK3128
arch/arm/boot/dts/rockchip/rk3128.dtsi | 7 +
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 156 ++++++++++++++----
2 files changed, 134 insertions(+), 29 deletions(-)
--
2.42.0
Commit 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") added ID
detection interrupt registers. However the current implementation assumes
that falling and rising edge interrupt are always enabled in registers
spanning over subsequent bits.
That is not the case for RK3128's version of the phy and this
implementation can't be used as-is, since there are bits with different
purpose in between.
This splits up the register definitions for id_det_en, id_det_en and
id_det_clr registers in rising and falling edge variants.
It's required as preparation to support RK3128's Innosilicon usb2 phy as
well in this driver and matches pretty much to what the vendor does, so I'm
not expecting issues for other SoCs with that change.
Signed-off-by: Alex Bee <[email protected]>
---
Changes in v3:
- rebased on linux-next
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 99 +++++++++++++------
1 file changed, 70 insertions(+), 29 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index a24d2af154df..b5a1d30df83a 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -123,9 +123,12 @@ struct rockchip_chg_det_reg {
* @disrise_en: host disconnect rise edge detection enable.
* @disrise_st: host disconnect rise edge detection state.
* @disrise_clr: host disconnect rise edge detection clear.
- * @id_det_en: id detection enable register.
- * @id_det_st: id detection state register.
- * @id_det_clr: id detection clear register.
+ * @idfall_det_en: id detection enable register, falling edge
+ * @idfall_det_st: id detection state register, falling edge
+ * @idfall_det_clr: id detection clear register, falling edge
+ * @idrise_det_en: id detection enable register, rising edge
+ * @idrise_det_st: id detection state register, rising edge
+ * @idrise_det_clr: id detection clear register, rising edge
* @ls_det_en: linestate detection enable register.
* @ls_det_st: linestate detection state register.
* @ls_det_clr: linestate detection clear register.
@@ -146,9 +149,12 @@ struct rockchip_usb2phy_port_cfg {
struct usb2phy_reg disrise_en;
struct usb2phy_reg disrise_st;
struct usb2phy_reg disrise_clr;
- struct usb2phy_reg id_det_en;
- struct usb2phy_reg id_det_st;
- struct usb2phy_reg id_det_clr;
+ struct usb2phy_reg idfall_det_en;
+ struct usb2phy_reg idfall_det_st;
+ struct usb2phy_reg idfall_det_clr;
+ struct usb2phy_reg idrise_det_en;
+ struct usb2phy_reg idrise_det_st;
+ struct usb2phy_reg idrise_det_clr;
struct usb2phy_reg ls_det_en;
struct usb2phy_reg ls_det_st;
struct usb2phy_reg ls_det_clr;
@@ -488,15 +494,27 @@ static int rockchip_usb2phy_init(struct phy *phy)
if (ret)
goto out;
- /* clear id status and enable id detect irq */
+ /* clear id status and enable id detect irqs */
ret = property_enable(rphy->grf,
- &rport->port_cfg->id_det_clr,
+ &rport->port_cfg->idfall_det_clr,
true);
if (ret)
goto out;
ret = property_enable(rphy->grf,
- &rport->port_cfg->id_det_en,
+ &rport->port_cfg->idrise_det_clr,
+ true);
+ if (ret)
+ goto out;
+
+ ret = property_enable(rphy->grf,
+ &rport->port_cfg->idfall_det_en,
+ true);
+ if (ret)
+ goto out;
+
+ ret = property_enable(rphy->grf,
+ &rport->port_cfg->idrise_det_en,
true);
if (ret)
goto out;
@@ -1030,11 +1048,16 @@ static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
bool id;
- if (!property_enabled(rphy->grf, &rport->port_cfg->id_det_st))
+ if (!property_enabled(rphy->grf, &rport->port_cfg->idfall_det_st) &&
+ !property_enabled(rphy->grf, &rport->port_cfg->idrise_det_st))
return IRQ_NONE;
/* clear id detect irq pending status */
- property_enable(rphy->grf, &rport->port_cfg->id_det_clr, true);
+ if (property_enabled(rphy->grf, &rport->port_cfg->idfall_det_st))
+ property_enable(rphy->grf, &rport->port_cfg->idfall_det_clr, true);
+
+ if (property_enabled(rphy->grf, &rport->port_cfg->idrise_det_st))
+ property_enable(rphy->grf, &rport->port_cfg->idrise_det_clr, true);
id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id);
@@ -1524,9 +1547,12 @@ static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
.bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
.bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
.bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
- .id_det_en = { 0x0680, 6, 5, 0, 3 },
- .id_det_st = { 0x0690, 6, 5, 0, 3 },
- .id_det_clr = { 0x06a0, 6, 5, 0, 3 },
+ .idfall_det_en = { 0x0680, 6, 6, 0, 1 },
+ .idfall_det_st = { 0x0690, 6, 6, 0, 1 },
+ .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 },
+ .idrise_det_en = { 0x0680, 5, 5, 0, 1 },
+ .idrise_det_st = { 0x0690, 5, 5, 0, 1 },
+ .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 },
.ls_det_en = { 0x0680, 2, 2, 0, 1 },
.ls_det_st = { 0x0690, 2, 2, 0, 1 },
.ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
@@ -1587,9 +1613,12 @@ static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = {
.bvalid_det_en = { 0x3020, 3, 2, 0, 3 },
.bvalid_det_st = { 0x3024, 3, 2, 0, 3 },
.bvalid_det_clr = { 0x3028, 3, 2, 0, 3 },
- .id_det_en = { 0x3020, 5, 4, 0, 3 },
- .id_det_st = { 0x3024, 5, 4, 0, 3 },
- .id_det_clr = { 0x3028, 5, 4, 0, 3 },
+ .idfall_det_en = { 0x3020, 5, 5, 0, 1 },
+ .idfall_det_st = { 0x3024, 5, 5, 0, 1 },
+ .idfall_det_clr = { 0x3028, 5, 5, 0, 1 },
+ .idrise_det_en = { 0x3020, 4, 4, 0, 1 },
+ .idrise_det_st = { 0x3024, 4, 4, 0, 1 },
+ .idrise_det_clr = { 0x3028, 4, 4, 0, 1 },
.ls_det_en = { 0x3020, 0, 0, 0, 1 },
.ls_det_st = { 0x3024, 0, 0, 0, 1 },
.ls_det_clr = { 0x3028, 0, 0, 0, 1 },
@@ -1634,9 +1663,12 @@ static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
.bvalid_det_en = { 0x0110, 3, 2, 0, 3 },
.bvalid_det_st = { 0x0114, 3, 2, 0, 3 },
.bvalid_det_clr = { 0x0118, 3, 2, 0, 3 },
- .id_det_en = { 0x0110, 5, 4, 0, 3 },
- .id_det_st = { 0x0114, 5, 4, 0, 3 },
- .id_det_clr = { 0x0118, 5, 4, 0, 3 },
+ .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
+ .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
+ .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
+ .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
+ .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
+ .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
.ls_det_en = { 0x0110, 0, 0, 0, 1 },
.ls_det_st = { 0x0114, 0, 0, 0, 1 },
.ls_det_clr = { 0x0118, 0, 0, 0, 1 },
@@ -1700,9 +1732,12 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
.bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
.bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
.bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
- .id_det_en = { 0xe3c0, 5, 4, 0, 3 },
- .id_det_st = { 0xe3e0, 5, 4, 0, 3 },
- .id_det_clr = { 0xe3d0, 5, 4, 0, 3 },
+ .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 },
+ .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 },
+ .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 },
+ .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 },
+ .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 },
+ .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 },
.utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
.utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
.utmi_id = { 0xe2ac, 8, 8, 0, 1 },
@@ -1739,9 +1774,12 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
.bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
.bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
.bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
- .id_det_en = { 0xe3c0, 10, 9, 0, 3 },
- .id_det_st = { 0xe3e0, 10, 9, 0, 3 },
- .id_det_clr = { 0xe3d0, 10, 9, 0, 3 },
+ .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 },
+ .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 },
+ .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 },
+ .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 },
+ .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 },
+ .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 },
.utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
.utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
.utmi_id = { 0xe2ac, 11, 11, 0, 1 },
@@ -1770,9 +1808,12 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
.bvalid_det_en = { 0x0080, 3, 2, 0, 3 },
.bvalid_det_st = { 0x0084, 3, 2, 0, 3 },
.bvalid_det_clr = { 0x0088, 3, 2, 0, 3 },
- .id_det_en = { 0x0080, 5, 4, 0, 3 },
- .id_det_st = { 0x0084, 5, 4, 0, 3 },
- .id_det_clr = { 0x0088, 5, 4, 0, 3 },
+ .idfall_det_en = { 0x0080, 5, 5, 0, 1 },
+ .idfall_det_st = { 0x0084, 5, 5, 0, 1 },
+ .idfall_det_clr = { 0x0088, 5, 5, 0, 1 },
+ .idrise_det_en = { 0x0080, 4, 4, 0, 1 },
+ .idrise_det_st = { 0x0084, 4, 4, 0, 1 },
+ .idrise_det_clr = { 0x0088, 4, 4, 0, 1 },
.utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
.utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
.utmi_id = { 0x00c0, 6, 6, 0, 1 },
--
2.42.0
Add the required AHB clocks for both the ehci and ohci controller.
Signed-off-by: Alex Bee <[email protected]>
---
arch/arm/boot/dts/rockchip/rk3128.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index 7bf557c99561..074dffa377cc 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -163,6 +163,7 @@ usb_host_ehci: usb@101c0000 {
compatible = "generic-ehci";
reg = <0x101c0000 0x20000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST2>;
phys = <&usb2phy_host>;
phy-names = "usb";
status = "disabled";
@@ -172,6 +173,7 @@ usb_host_ohci: usb@101e0000 {
compatible = "generic-ohci";
reg = <0x101e0000 0x20000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST2>;
phys = <&usb2phy_host>;
phy-names = "usb";
status = "disabled";
--
2.42.0
Am Sonntag, 19. November 2023, 13:13:36 CET schrieb Alex Bee:
> Commit 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") added ID
> detection interrupt registers. However the current implementation assumes
> that falling and rising edge interrupt are always enabled in registers
> spanning over subsequent bits.
> That is not the case for RK3128's version of the phy and this
> implementation can't be used as-is, since there are bits with different
> purpose in between.
>
> This splits up the register definitions for id_det_en, id_det_en and
> id_det_clr registers in rising and falling edge variants.
> It's required as preparation to support RK3128's Innosilicon usb2 phy as
> well in this driver and matches pretty much to what the vendor does, so I'm
> not expecting issues for other SoCs with that change.
>
> Signed-off-by: Alex Bee <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
On Sun, 19 Nov 2023 13:13:35 +0100, Alex Bee wrote:
> While interestingly the DT-binding for the Innosilicon usb phy found in
> RK3128 SoC exists already and it is exposed in the SoC DT, it has never
> been added to the driver.
> This patch-set adds support for this early version of the phy and does
> some DT-fixups in order to make the 2-port host/otg phy and the respective
> controllers work.
>
> [...]
Applied, thanks!
[3/5] ARM: dts: rockchip: Add USB host clocks for RK3128
commit: 759d6bd9ef94f0e658202947d44b939c6e3ed363
[4/5] ARM: dts: rockchip: Add dwc2 otg fifo siztes for RK3128
commit: 4b12245e59efea81e19d1aa118f6f835b3e27b3a
[5/5] ARM: dts: rockchip: Make usbphy the parent of SCLK_USB480M for RK3128
commit: fd610e604837936440ef7c64ab6998b004631647
The rk3128 binding and the phys is already defined in the binding
and devicetree, so I've picked up these, as they're independent of
the phy changes themself.
Best regards,
--
Heiko Stuebner <[email protected]>
On Sun, 19 Nov 2023 13:13:35 +0100, Alex Bee wrote:
> While interestingly the DT-binding for the Innosilicon usb phy found in
> RK3128 SoC exists already and it is exposed in the SoC DT, it has never
> been added to the driver.
> This patch-set adds support for this early version of the phy and does
> some DT-fixups in order to make the 2-port host/otg phy and the respective
> controllers work.
>
> [...]
Applied, thanks!
[1/5] phy: rockchip-inno-usb2: Split ID interrupt phy registers
commit: 2fda59099462ee700e424ba3ac928d13ad6389a8
[2/5] phy: phy-rockchip-inno-usb2: Add RK3128 support
commit: 62ff41017e147472b07de6125c3be82ce02a8dd7
Best regards,
--
~Vinod