Hi,
This small series has some fixes for the PCIe nodes in Qcom DTS.
- Mani
Manivannan Sadhasivam (3):
ARM: dts: qcom: Use "pcie" as the node name instead of "pci"
arm64: dts: qcom: Use "pcie" as the node name instead of "pci"
arm64: dts: qcom: sa8775p: Add missing space between node name and
braces
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 2 +-
arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi | 2 +-
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 2 +-
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 6 +++---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++--
17 files changed, 31 insertions(+), 31 deletions(-)
--
2.25.1
Qcom SoCs doesn't support the legacy PCI, but only PCIe. So use the correct
node name for the controller instances.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 2 +-
arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi | 2 +-
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 2 +-
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 6 +++---
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
index 59fd86b9fb47..fa3a0f72a18e 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
@@ -1472,7 +1472,7 @@ gfx3d1: iommu@7d00000 {
qcom,ncb = <3>;
};
- pcie: pci@1b500000 {
+ pcie: pcie@1b500000 {
compatible = "qcom,pcie-apq8064";
reg = <0x1b500000 0x1000>,
<0x1b502000 0x80>,
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi
index 468ebc40d2ad..374af6dd360a 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi
@@ -98,7 +98,7 @@ flash@0 {
};
};
- pci@40000000 {
+ pcie@40000000 {
status = "okay";
perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
index 9844e0b7cff9..6cbbccda5cf5 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
@@ -417,7 +417,7 @@ restart@4ab000 {
reg = <0x4ab000 0x4>;
};
- pcie0: pci@40000000 {
+ pcie0: pcie@40000000 {
compatible = "qcom,pcie-ipq4019";
reg = <0x40000000 0xf1d>,
<0x40000f20 0xa8>,
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
index 6198f42f6a9c..7c233b00a2dd 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
@@ -1076,7 +1076,7 @@ sata_phy: sata-phy@1b400000 {
status = "disabled";
};
- pcie0: pci@1b500000 {
+ pcie0: pcie@1b500000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b500000 0x1000
0x1b502000 0x80
@@ -1127,7 +1127,7 @@ pcie0: pci@1b500000 {
perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
};
- pcie1: pci@1b700000 {
+ pcie1: pcie@1b700000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b700000 0x1000
0x1b702000 0x80
@@ -1178,7 +1178,7 @@ pcie1: pci@1b700000 {
perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
};
- pcie2: pci@1b900000 {
+ pcie2: pcie@1b900000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b900000 0x1000
0x1b902000 0x80
--
2.25.1
Add missing space between node name and braces to match the style.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index d73fc3983709..8ba6785038fa 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -2409,7 +2409,7 @@ arch_timer: timer {
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
- pcie0: pcie@1c00000{
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sa8775p";
reg = <0x0 0x01c00000 0x0 0x3000>,
<0x0 0x40000000 0x0 0xf20>,
@@ -2509,7 +2509,7 @@ pcie0_phy: phy@1c04000 {
status = "disabled";
};
- pcie1: pcie@1c10000{
+ pcie1: pcie@1c10000 {
compatible = "qcom,pcie-sa8775p";
reg = <0x0 0x01c10000 0x0 0x3000>,
<0x0 0x60000000 0x0 0xf20>,
--
2.25.1
Qcom SoCs doesn't support the legacy PCI, but only PCIe. So use the correct
node name for the controller instances.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++--
13 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index e59b9df96c7e..c649744e8751 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -731,7 +731,7 @@ qrtr_requests {
};
};
- pcie0: pci@20000000 {
+ pcie0: pcie@20000000 {
compatible = "qcom,pcie-ipq6018";
reg = <0x0 0x20000000 0x0 0xf1d>,
<0x0 0x20000f20 0x0 0xa8>,
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2f275c84e566..c6a96d8c9856 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -781,7 +781,7 @@ frame@b128000 {
};
};
- pcie1: pci@10000000 {
+ pcie1: pcie@10000000 {
compatible = "qcom,pcie-ipq8074";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
@@ -842,7 +842,7 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
status = "disabled";
};
- pcie0: pci@20000000 {
+ pcie0: pcie@20000000 {
compatible = "qcom,pcie-ipq8074-gen3";
reg = <0x20000000 0xf1d>,
<0x20000f20 0xa8>,
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index b485bf925ce6..b6a3e6afaefd 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -933,7 +933,7 @@ anoc2_smmu: iommu@16c0000 {
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
reg = <0x01c00000 0x2000>,
<0x1b000000 0xf1d>,
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 2721f32dfb71..6ac64ce9bb68 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -1461,7 +1461,7 @@ glink-edge {
};
};
- pcie: pci@10000000 {
+ pcie: pcie@10000000 {
compatible = "qcom,pcie-qcs404";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index b6a93b11cbbd..d73fc3983709 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -2409,7 +2409,7 @@ arch_timer: timer {
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
- pcie0: pci@1c00000{
+ pcie0: pcie@1c00000{
compatible = "qcom,pcie-sa8775p";
reg = <0x0 0x01c00000 0x0 0x3000>,
<0x0 0x40000000 0x0 0xf20>,
@@ -2509,7 +2509,7 @@ pcie0_phy: phy@1c04000 {
status = "disabled";
};
- pcie1: pci@1c10000{
+ pcie1: pcie@1c10000{
compatible = "qcom,pcie-sa8775p";
reg = <0x0 0x01c10000 0x0 0x3000>,
<0x0 0x60000000 0x0 0xf20>,
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 66f1eb83cca7..fb5e735247e7 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2126,7 +2126,7 @@ wifi: wifi@17a10040 {
qcom,smem-state-names = "wlan-smp2p-out";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sc7280";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index a34f438ef2d9..8bcc8c0bb0d0 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -1684,7 +1684,7 @@ mmss_noc: interconnect@1740000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sc8180x";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
@@ -1781,7 +1781,7 @@ pcie0_phy: phy@1c06000 {
status = "disabled";
};
- pcie3: pci@1c08000 {
+ pcie3: pcie@1c08000 {
compatible = "qcom,pcie-sc8180x";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
@@ -1879,7 +1879,7 @@ pcie3_phy: phy@1c0c000 {
status = "disabled";
};
- pcie1: pci@1c10000 {
+ pcie1: pcie@1c10000 {
compatible = "qcom,pcie-sc8180x";
reg = <0 0x01c10000 0 0x3000>,
<0 0x68000000 0 0xf1d>,
@@ -1977,7 +1977,7 @@ pcie1_phy: phy@1c16000 {
status = "disabled";
};
- pcie2: pci@1c18000 {
+ pcie2: pcie@1c18000 {
compatible = "qcom,pcie-sc8180x";
reg = <0 0x01c18000 0 0x3000>,
<0 0x70000000 0 0xf1d>,
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index bf5e6eb9d313..cb3bfd262851 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2306,7 +2306,7 @@ opp-4 {
};
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sdm845";
reg = <0 0x01c00000 0 0x2000>,
<0 0x60000000 0 0xf1d>,
@@ -2405,7 +2405,7 @@ pcie0_phy: phy@1c06000 {
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sdm845";
reg = <0 0x01c08000 0 0x2000>,
<0 0x40000000 0 0xf1d>,
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 97623af13464..43d56968a382 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1824,7 +1824,7 @@ dma@10a2000 {
<0x0 0x010ad000 0x0 0x3000>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sm8150";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
@@ -1915,7 +1915,7 @@ pcie0_phy: phy@1c06000 {
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sm8150";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index be970472f6c4..c1b7f9620ec6 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2123,7 +2123,7 @@ mmss_noc: interconnect@1740000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sm8250";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
@@ -2227,7 +2227,7 @@ pcie0_phy: phy@1c06000 {
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sm8250";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
@@ -2328,7 +2328,7 @@ pcie1_phy: phy@1c0e000 {
status = "disabled";
};
- pcie2: pci@1c10000 {
+ pcie2: pcie@1c10000 {
compatible = "qcom,pcie-sm8250";
reg = <0 0x01c10000 0 0x3000>,
<0 0x64000000 0 0xf1d>,
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index b46236235b7f..f4b8439200f5 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1498,7 +1498,7 @@ mmss_noc: interconnect@1740000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sm8350";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
@@ -1591,7 +1591,7 @@ pcie0_phy: phy@1c06000 {
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sm8350";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 1783fa78bdbc..44a61fa2cc49 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1739,7 +1739,7 @@ spi14: spi@a98000 {
};
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sm8450-pcie0";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
@@ -1848,7 +1848,7 @@ pcie0_phy: phy@1c06000 {
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sm8450-pcie1";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 7b9ddde0b2c9..baa8540868a4 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1677,7 +1677,7 @@ mmss_noc: interconnect@1780000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,pcie-sm8550";
reg = <0 0x01c00000 0 0x3000>,
@@ -1768,7 +1768,7 @@ pcie0_phy: phy@1c06000 {
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
device_type = "pci";
compatible = "qcom,pcie-sm8550";
reg = <0x0 0x01c08000 0x0 0x3000>,
--
2.25.1
On Wed, 06 Dec 2023 19:25:37 +0530, Manivannan Sadhasivam wrote:
> This small series has some fixes for the PCIe nodes in Qcom DTS.
>
> - Mani
>
> Manivannan Sadhasivam (3):
> ARM: dts: qcom: Use "pcie" as the node name instead of "pci"
> arm64: dts: qcom: Use "pcie" as the node name instead of "pci"
> arm64: dts: qcom: sa8775p: Add missing space between node name and
> braces
>
> [...]
Applied, thanks!
[2/3] arm64: dts: qcom: Use "pcie" as the node name instead of "pci"
commit: 052c9a1f1400f1b3fe9555bd029ee9a8a0db3cd0
[3/3] arm64: dts: qcom: sa8775p: Add missing space between node name and braces
commit: 809ec4c5a5ab8ac080adbd9624d0040850725acc
Best regards,
--
Bjorn Andersson <[email protected]>