2024-02-14 17:58:24

by Easwar Hariharan

[permalink] [raw]
Subject: [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata

Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
suffers from all the same errata.

CC: [email protected] # 5.15+
Signed-off-by: Easwar Hariharan <[email protected]>
---
changelog:
v1->v2:
* v1: https://lore.kernel.org/linux-arm-kernel/[email protected]/T/#u
* Consistently use MICROSOFT throughout
---
Documentation/arch/arm64/silicon-errata.rst | 7 +++++++
arch/arm64/include/asm/cputype.h | 4 ++++
arch/arm64/kernel/cpu_errata.c | 3 +++
3 files changed, 14 insertions(+)

diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index e8c2ce1f9df6..45a7f4932fe0 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -243,3 +243,10 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ASR | ASR8601 | #8601001 | N/A |
+----------------+-----------------+-----------------+-----------------------------+
++----------------+-----------------+-----------------+-----------------------------+
+| Microsoft | Azure Cobalt 100| #2139208 | ARM64_ERRATUM_2139208 |
++----------------+-----------------+-----------------+-----------------------------+
+| Microsoft | Azure Cobalt 100| #2067961 | ARM64_ERRATUM_2067961 |
++----------------+-----------------+-----------------+-----------------------------+
+| Microsoft | Azure Cobalt 100| #2253138 | ARM64_ERRATUM_2253138 |
++----------------+-----------------+-----------------+-----------------------------+
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 7c7493cb571f..52f076afeb96 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -61,6 +61,7 @@
#define ARM_CPU_IMP_HISI 0x48
#define ARM_CPU_IMP_APPLE 0x61
#define ARM_CPU_IMP_AMPERE 0xC0
+#define ARM_CPU_IMP_MICROSOFT 0x6D

#define ARM_CPU_PART_AEM_V8 0xD0F
#define ARM_CPU_PART_FOUNDATION 0xD00
@@ -135,6 +136,8 @@

#define AMPERE_CPU_PART_AMPERE1 0xAC3

+#define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */
+
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
@@ -193,6 +196,7 @@
#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
+#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)

/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 967c7c7a4e7d..76b8dd37092a 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -374,6 +374,7 @@ static const struct midr_range erratum_1463225[] = {
static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
#ifdef CONFIG_ARM64_ERRATUM_2139208
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
+ MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
#endif
#ifdef CONFIG_ARM64_ERRATUM_2119858
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
@@ -387,6 +388,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
static const struct midr_range tsb_flush_fail_cpus[] = {
#ifdef CONFIG_ARM64_ERRATUM_2067961
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
+ MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
#endif
#ifdef CONFIG_ARM64_ERRATUM_2054223
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
@@ -399,6 +401,7 @@ static const struct midr_range tsb_flush_fail_cpus[] = {
static struct midr_range trbe_write_out_of_range_cpus[] = {
#ifdef CONFIG_ARM64_ERRATUM_2253138
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
+ MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
#endif
#ifdef CONFIG_ARM64_ERRATUM_2224489
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
--
2.34.1



2024-02-14 18:59:42

by Mark Rutland

[permalink] [raw]
Subject: Re: [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata

On Wed, Feb 14, 2024 at 05:55:18PM +0000, Easwar Hariharan wrote:
> Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
> implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
> suffers from all the same errata.
>
> CC: [email protected] # 5.15+
> Signed-off-by: Easwar Hariharan <[email protected]>

Acked-by: Mark Rutland <[email protected]>

I assume that Catalin/Will will take this through the arm64 tree.

Mark.

> ---
> changelog:
> v1->v2:
> * v1: https://lore.kernel.org/linux-arm-kernel/[email protected]/T/#u
> * Consistently use MICROSOFT throughout
> ---
> Documentation/arch/arm64/silicon-errata.rst | 7 +++++++
> arch/arm64/include/asm/cputype.h | 4 ++++
> arch/arm64/kernel/cpu_errata.c | 3 +++
> 3 files changed, 14 insertions(+)
>
> diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
> index e8c2ce1f9df6..45a7f4932fe0 100644
> --- a/Documentation/arch/arm64/silicon-errata.rst
> +++ b/Documentation/arch/arm64/silicon-errata.rst
> @@ -243,3 +243,10 @@ stable kernels.
> +----------------+-----------------+-----------------+-----------------------------+
> | ASR | ASR8601 | #8601001 | N/A |
> +----------------+-----------------+-----------------+-----------------------------+
> ++----------------+-----------------+-----------------+-----------------------------+
> +| Microsoft | Azure Cobalt 100| #2139208 | ARM64_ERRATUM_2139208 |
> ++----------------+-----------------+-----------------+-----------------------------+
> +| Microsoft | Azure Cobalt 100| #2067961 | ARM64_ERRATUM_2067961 |
> ++----------------+-----------------+-----------------+-----------------------------+
> +| Microsoft | Azure Cobalt 100| #2253138 | ARM64_ERRATUM_2253138 |
> ++----------------+-----------------+-----------------+-----------------------------+
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index 7c7493cb571f..52f076afeb96 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -61,6 +61,7 @@
> #define ARM_CPU_IMP_HISI 0x48
> #define ARM_CPU_IMP_APPLE 0x61
> #define ARM_CPU_IMP_AMPERE 0xC0
> +#define ARM_CPU_IMP_MICROSOFT 0x6D
>
> #define ARM_CPU_PART_AEM_V8 0xD0F
> #define ARM_CPU_PART_FOUNDATION 0xD00
> @@ -135,6 +136,8 @@
>
> #define AMPERE_CPU_PART_AMPERE1 0xAC3
>
> +#define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */
> +
> #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
> #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
> #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
> @@ -193,6 +196,7 @@
> #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
> #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
> #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
> +#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)
>
> /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
> #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 967c7c7a4e7d..76b8dd37092a 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -374,6 +374,7 @@ static const struct midr_range erratum_1463225[] = {
> static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
> #ifdef CONFIG_ARM64_ERRATUM_2139208
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
> #endif
> #ifdef CONFIG_ARM64_ERRATUM_2119858
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> @@ -387,6 +388,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
> static const struct midr_range tsb_flush_fail_cpus[] = {
> #ifdef CONFIG_ARM64_ERRATUM_2067961
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
> #endif
> #ifdef CONFIG_ARM64_ERRATUM_2054223
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> @@ -399,6 +401,7 @@ static const struct midr_range tsb_flush_fail_cpus[] = {
> static struct midr_range trbe_write_out_of_range_cpus[] = {
> #ifdef CONFIG_ARM64_ERRATUM_2253138
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
> #endif
> #ifdef CONFIG_ARM64_ERRATUM_2224489
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> --
> 2.34.1
>

2024-02-14 20:58:38

by Oliver Upton

[permalink] [raw]
Subject: Re: [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata

On Wed, Feb 14, 2024 at 05:55:18PM +0000, Easwar Hariharan wrote:
> Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
> implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
> suffers from all the same errata.
>
> CC: [email protected] # 5.15+
> Signed-off-by: Easwar Hariharan <[email protected]>

Reviewed-by: Oliver Upton <[email protected]>

--
Thanks,
Oliver

2024-02-15 06:52:57

by Anshuman Khandual

[permalink] [raw]
Subject: Re: [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata



On 2/14/24 23:25, Easwar Hariharan wrote:
> Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
> implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
> suffers from all the same errata.
>
> CC: [email protected] # 5.15+
> Signed-off-by: Easwar Hariharan <[email protected]>

Reviewed-by: Anshuman Khandual <[email protected]>

> ---
> changelog:
> v1->v2:
> * v1: https://lore.kernel.org/linux-arm-kernel/[email protected]/T/#u
> * Consistently use MICROSOFT throughout
> ---
> Documentation/arch/arm64/silicon-errata.rst | 7 +++++++
> arch/arm64/include/asm/cputype.h | 4 ++++
> arch/arm64/kernel/cpu_errata.c | 3 +++
> 3 files changed, 14 insertions(+)
>
> diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
> index e8c2ce1f9df6..45a7f4932fe0 100644
> --- a/Documentation/arch/arm64/silicon-errata.rst
> +++ b/Documentation/arch/arm64/silicon-errata.rst
> @@ -243,3 +243,10 @@ stable kernels.
> +----------------+-----------------+-----------------+-----------------------------+
> | ASR | ASR8601 | #8601001 | N/A |
> +----------------+-----------------+-----------------+-----------------------------+
> ++----------------+-----------------+-----------------+-----------------------------+
> +| Microsoft | Azure Cobalt 100| #2139208 | ARM64_ERRATUM_2139208 |
> ++----------------+-----------------+-----------------+-----------------------------+
> +| Microsoft | Azure Cobalt 100| #2067961 | ARM64_ERRATUM_2067961 |
> ++----------------+-----------------+-----------------+-----------------------------+
> +| Microsoft | Azure Cobalt 100| #2253138 | ARM64_ERRATUM_2253138 |
> ++----------------+-----------------+-----------------+-----------------------------+
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index 7c7493cb571f..52f076afeb96 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -61,6 +61,7 @@
> #define ARM_CPU_IMP_HISI 0x48
> #define ARM_CPU_IMP_APPLE 0x61
> #define ARM_CPU_IMP_AMPERE 0xC0
> +#define ARM_CPU_IMP_MICROSOFT 0x6D
>
> #define ARM_CPU_PART_AEM_V8 0xD0F
> #define ARM_CPU_PART_FOUNDATION 0xD00
> @@ -135,6 +136,8 @@
>
> #define AMPERE_CPU_PART_AMPERE1 0xAC3
>
> +#define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */
> +
> #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
> #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
> #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
> @@ -193,6 +196,7 @@
> #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
> #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
> #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
> +#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)
>
> /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
> #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 967c7c7a4e7d..76b8dd37092a 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -374,6 +374,7 @@ static const struct midr_range erratum_1463225[] = {
> static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
> #ifdef CONFIG_ARM64_ERRATUM_2139208
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
> #endif
> #ifdef CONFIG_ARM64_ERRATUM_2119858
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> @@ -387,6 +388,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
> static const struct midr_range tsb_flush_fail_cpus[] = {
> #ifdef CONFIG_ARM64_ERRATUM_2067961
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
> #endif
> #ifdef CONFIG_ARM64_ERRATUM_2054223
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
> @@ -399,6 +401,7 @@ static const struct midr_range tsb_flush_fail_cpus[] = {
> static struct midr_range trbe_write_out_of_range_cpus[] = {
> #ifdef CONFIG_ARM64_ERRATUM_2253138
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
> + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
> #endif
> #ifdef CONFIG_ARM64_ERRATUM_2224489
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),

2024-02-15 09:57:38

by Marc Zyngier

[permalink] [raw]
Subject: Re: [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata

On Wed, 14 Feb 2024 17:55:18 +0000,
Easwar Hariharan <[email protected]> wrote:
>
> Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
> implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
> suffers from all the same errata.
>
> CC: [email protected] # 5.15+
> Signed-off-by: Easwar Hariharan <[email protected]>

Thanks for respinning this.

Acked-by: Marc Zyngier <[email protected]>

M.

--
Without deviation from the norm, progress is not possible.

2024-02-15 12:47:31

by Will Deacon

[permalink] [raw]
Subject: Re: [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata

On Wed, 14 Feb 2024 17:55:18 +0000, Easwar Hariharan wrote:
> Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
> implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
> suffers from all the same errata.
>
>

Applied to arm64 (for-next/fixes), thanks!

[1/1] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata
https://git.kernel.org/arm64/c/fb091ff39479

Cheers,
--
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev