2024-02-16 01:45:43

by Hojin Nam

Subject: [PATCH v3] perf: CXL: fix CPMU filter value mask length

From: Hojin Nam <[email protected]>

CPMU filter value is described as 4B length in CXL r3.0 8.2.7.2.2.
However, it is used as 2B length in code and comments.

Reviewed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Hojin Nam <[email protected]>
---

Hi Will,
Sorry, I think whitespace-damage occurred while sending the patch.
I returned space to tab in the code below line 642, thank you!

Changes since v2:
- Return damaged whitespace to tabs (Will)

Changes since v1:
- Remove Fixes tag (Jonathan)
- Repair broken sign off (Jonathan)

drivers/perf/cxl_pmu.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c
index 365d964b0f6a..ca5e92f28b4a 100644
--- a/drivers/perf/cxl_pmu.c
+++ b/drivers/perf/cxl_pmu.c
@@ -59,7 +59,7 @@
#define CXL_PMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK GENMASK_ULL(63, 59)

#define CXL_PMU_FILTER_CFG_REG(n, f) (0x400 + 4 * ((f) + (n) * 8))
-#define CXL_PMU_FILTER_CFG_VALUE_MSK GENMASK(15, 0)
+#define CXL_PMU_FILTER_CFG_VALUE_MSK GENMASK(31, 0)

#define CXL_PMU_COUNTER_REG(n) (0xc00 + 8 * (n))

@@ -314,9 +314,9 @@ static bool cxl_pmu_config1_get_edge(struct perf_event *event)
}

/*
- * CPMU specification allows for 8 filters, each with a 16 bit value...
- * So we need to find 8x16bits to store it in.
- * As the value used for disable is 0xffff, a separate enable switch
+ * CPMU specification allows for 8 filters, each with a 32 bit value...
+ * So we need to find 8x32bits to store it in.
+ * As the value used for disable is 0xffff_ffff, a separate enable switch
* is needed.
*/

@@ -642,7 +642,7 @@ static void cxl_pmu_event_start(struct perf_event *event, int flags)
if (cxl_pmu_config1_hdm_filter_en(event))
cfg = cxl_pmu_config2_get_hdm_decoder(event);
else
- cfg = GENMASK(15, 0); /* No filtering if 0xFFFF_FFFF */
+ cfg = GENMASK(31, 0); /* No filtering if 0xFFFF_FFFF */
writeq(cfg, base + CXL_PMU_FILTER_CFG_REG(hwc->idx, 0));
}

--
2.34.1

2024-02-20 14:09:26

by Will Deacon

Subject: Re: [PATCH v3] perf: CXL: fix CPMU filter value mask length

On Fri, 16 Feb 2024 10:45:22 +0900, [email protected] wrote:
> From: Hojin Nam <[email protected]>
>
> CPMU filter value is described as 4B length in CXL r3.0 8.2.7.2.2.
> However, it is used as 2B length in code and comments.
>
>

Applied to arm64 (for-next/fixes), thanks!

[1/1] perf: CXL: fix CPMU filter value mask length
https://git.kernel.org/arm64/c/802379b8f9e1

Cheers,
--
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev