This adds register fields for ID_AA64DFR1_EL1 as per the definitions based
on DDI0601 2023-12.
Cc: Catalin Marinas <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: Mark Brown <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Anshuman Khandual <[email protected]>
---
This applies on v6.8-rc5
Changes in V2:
- Added enumerated values for DPFZS field per Mark
Changes in V1:
https://lore.kernel.org/all/[email protected]/
arch/arm64/tools/sysreg | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 4c9b67934367..dd693f992832 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1251,7 +1251,36 @@ EndEnum
EndSysreg
Sysreg ID_AA64DFR1_EL1 3 0 0 5 1
-Res0 63:0
+Field 63:56 ABL_CMPs
+UnsignedEnum 55:52 DPFZS
+ 0b0000 IGNR
+ 0b0001 FRZN
+EndEnum
+UnsignedEnum 51:48 EBEP
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+UnsignedEnum 47:44 ITE
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+UnsignedEnum 43:40 ABLE
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+UnsignedEnum 39:36 PMICNTR
+ 0b0000 NI
+ 0b0001 IMP
+EndEnum
+UnsignedEnum 35:32 SPMU
+ 0b0000 NI
+ 0b0001 IMP
+ 0b0010 IMP_SPMZR
+EndEnum
+Field 31:24 CTX_CMPs
+Field 23:16 WRPs
+Field 15:8 BRPs
+Field 7:0 SYSPMUID
EndSysreg
Sysreg ID_AA64AFR0_EL1 3 0 0 5 4
--
2.25.1
On Tue, Feb 20, 2024 at 08:02:03AM +0530, Anshuman Khandual wrote:
> This adds register fields for ID_AA64DFR1_EL1 as per the definitions based
> on DDI0601 2023-12.
Reviewed-by: Mark Brown <[email protected]>
On Tue, 20 Feb 2024 08:02:03 +0530, Anshuman Khandual wrote:
> This adds register fields for ID_AA64DFR1_EL1 as per the definitions based
> on DDI0601 2023-12.
>
>
Applied to arm64 (for-next/sysreg), thanks!
[1/1] arm64/sysreg: Add register fields for ID_AA64DFR1_EL1
https://git.kernel.org/arm64/c/fdd867fe9b32
--
Catalin