This updates ID_DFR0_EL1.PerfMon and ID_DFR0_EL1.CopDbg register fields as
per the definitions based on DDI0601 2023-12.
Cc: Catalin Marinas <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: Mark Brown <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Anshuman Khandual <[email protected]>
---
This applies on v6.8-rc5
Changes in V2:
- Split ID_DFR0_EL1 changes in this patch and updated PerfMon per Mark
Changes in V1:
https://lore.kernel.org/all/[email protected]/
arch/arm64/tools/sysreg | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index dd693f992832..a9cab2b730a3 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -200,6 +200,7 @@ UnsignedEnum 27:24 PerfMon
0b0110 PMUv3p5
0b0111 PMUv3p7
0b1000 PMUv3p8
+ 0b1001 PMUv3p9
0b1111 IMPDEF
EndEnum
Enum 23:20 MProfDbg
@@ -231,6 +232,7 @@ Enum 3:0 CopDbg
0b1000 Debugv8p2
0b1001 Debugv8p4
0b1010 Debugv8p8
+ 0b1011 Debugv8p9
EndEnum
EndSysreg
--
2.25.1
On Tue, Feb 20, 2024 at 08:23:43AM +0530, Anshuman Khandual wrote:
> This updates ID_DFR0_EL1.PerfMon and ID_DFR0_EL1.CopDbg register fields as
> per the definitions based on DDI0601 2023-12.
Reviewed-by: Mark Brown <[email protected]>
On Tue, 20 Feb 2024 08:23:43 +0530, Anshuman Khandual wrote:
> This updates ID_DFR0_EL1.PerfMon and ID_DFR0_EL1.CopDbg register fields as
> per the definitions based on DDI0601 2023-12.
>
>
Applied to arm64 (for-next/sysreg), thanks!
[1/1] arm64/sysreg: Update ID_DFR0_EL1 register fields
https://git.kernel.org/arm64/c/7accfaad89d7
--
Catalin