Due to some hardware changes, SA8775P has set the NO_SNOOP attribute
in its TLP for all the PCIe controllers. NO_SNOOP attribute when set,
the requester is indicating that no cache coherency issues exist for
the addressed memory on the host i.e., memory is not cached. But in
reality, requester cannot assume this unless there is a complete
control/visibility over the addressed memory on the host.
And worst case, if the memory is cached on the host, it may lead to
memory corruption issues. It should be noted that the caching of memory
on the host is not solely dependent on the NO_SNOOP attribute in TLP.
So to avoid the corruption, this patch overrides the NO_SNOOP attribute
by setting the PCIE_PARF_NO_SNOOP_OVERIDE register. This patch is not
needed for other upstream supported platforms since they do not set
NO_SNOOP attribute by default.
This series is to enable cache snooping logic in both RC and EP driver
and add the "dma-coherent" property in dtsi to support cache coherency
in SA8775P platform.
Dependency
----------
Depends on:
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/ [1]
V5 -> V6:
- updated commit message as per comments
- added Kdoc comments in patch1
- change variable name from enable_cache_snoop to
override_no_snoop
- sort reg offset define in patch2
V4 -> V5:
- Updated commit message in both Patch1 and patch2
- change variable name from no_snoop_override to
enable_cache_snoop
- rebased patch2 on top of [1]
v3 -> v4:
- added new cfg(cfg_1_34_0) for SA8775P in both RC and EP driver.
- populated a flag in the data structures instead of doing
of_device_is_compatible() in both RC and EP patch.
- update commit mesaage and added reveiwed-by tag in commit message
in dtsi patch.
v2 -> v3:
- update commit message(8755 -> 8775).
v1 -> v2:
- update cover letter with explanation.
- define each of these bits and ORing at usage time rather than
directly writing value in register.
Mrinmay Sarkar (3):
PCI: qcom: Override NO_SNOOP attribute for SA8775P RC
PCI: qcom-ep: Override NO_SNOOP attribute for SA8775P EP
arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherent
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 +
drivers/pci/controller/dwc/pcie-qcom-ep.c | 20 +++++++++++++++++---
drivers/pci/controller/dwc/pcie-qcom.c | 25 ++++++++++++++++++++++++-
3 files changed, 42 insertions(+), 4 deletions(-)
--
2.7.4
The PCIe EP controller on SA8775P supports cache coherency, hence add
the "dma-coherent" property to mark it as such.
Signed-off-by: Mrinmay Sarkar <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index d9802027..53c31c7 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3713,6 +3713,7 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
+ dma-coherent;
iommus = <&pcie_smmu 0x0000 0x7f>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "core";
--
2.7.4
On 06/03/2024 14:11, Mrinmay Sarkar wrote:
> The PCIe EP controller on SA8775P supports cache coherency, hence add
> the "dma-coherent" property to mark it as such.
>
> Signed-off-by: Mrinmay Sarkar <[email protected]>
> Reviewed-by: Manivannan Sadhasivam <[email protected]>
> ---
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof