Some improvement for audiomix driver:
Add CLK_SET_RATE_PARENT flags for clocks
Correct parent clock for earc_phy and audpll clocks.
Add reset controller for EARC function, use the auxiliary device
framework:
https://lore.kernel.org/lkml/[email protected]/
changes in v7:
- add property "#reset-cells" exist check
- change the reset driver to be specific for 8MP-audiomix
remove the design for general usage.
changes in v6:
- fix type for "correct"
- fix coding style for " * adev"
changes in v5:
- fix miss header issue reported by kernel test robot
- use scoped free
changes in v4:
- use auxiliary device framework for reset controller driver.
- drop syscon and simple-mfd related changes in v3
changes in v3:
- separate reset driver to driver/reset/
- add binding doc for reset driver.
- modify imx8mp.dtsi accordingly
changes in v2:
- add more info in commit messages
Shengjiu Wang (5):
dt-bindings: clock: imx8mp: Add #reset-cells property
clk: imx: clk-audiomix: Add reset controller
reset: imx8mp-audiomix: Add AudioMix Block Control reset driver
clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocks
clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpll
.../bindings/clock/imx8mp-audiomix.yaml | 3 +
drivers/clk/imx/Kconfig | 1 +
drivers/clk/imx/clk-imx8mp-audiomix.c | 86 ++++++++++++++-
drivers/reset/Kconfig | 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-imx8mp-audiomix.c | 103 ++++++++++++++++++
6 files changed, 196 insertions(+), 6 deletions(-)
create mode 100644 drivers/reset/reset-imx8mp-audiomix.c
--
2.34.1
According to Reference Manual of i.MX8MP
The parent clock of "earc_phy" is "sai_pll_out_div2",
The parent clock of "audpll" is "osc_24m".
Add CLK_GATE_PARENT() macro for usage of specifying parent clock.
Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block control")
Signed-off-by: Shengjiu Wang <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
---
drivers/clk/imx/clk-imx8mp-audiomix.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c
index 7fd336a96cfe..50ad5873c990 100644
--- a/drivers/clk/imx/clk-imx8mp-audiomix.c
+++ b/drivers/clk/imx/clk-imx8mp-audiomix.c
@@ -156,6 +156,15 @@ static const struct clk_parent_data clk_imx8mp_audiomix_pll_bypass_sels[] = {
PDM_SEL, 2, 0 \
}
+#define CLK_GATE_PARENT(gname, cname, pname) \
+ { \
+ gname"_cg", \
+ IMX8MP_CLK_AUDIOMIX_##cname, \
+ { .fw_name = pname, .name = pname }, NULL, 1, \
+ CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32), \
+ 1, IMX8MP_CLK_AUDIOMIX_##cname % 32 \
+ }
+
struct clk_imx8mp_audiomix_sel {
const char *name;
int clkid;
@@ -173,14 +182,14 @@ static struct clk_imx8mp_audiomix_sel sels[] = {
CLK_GATE("earc", EARC_IPG),
CLK_GATE("ocrama", OCRAMA_IPG),
CLK_GATE("aud2htx", AUD2HTX_IPG),
- CLK_GATE("earc_phy", EARC_PHY),
+ CLK_GATE_PARENT("earc_phy", EARC_PHY, "sai_pll_out_div2"),
CLK_GATE("sdma2", SDMA2_ROOT),
CLK_GATE("sdma3", SDMA3_ROOT),
CLK_GATE("spba2", SPBA2_ROOT),
CLK_GATE("dsp", DSP_ROOT),
CLK_GATE("dspdbg", DSPDBG_ROOT),
CLK_GATE("edma", EDMA_ROOT),
- CLK_GATE("audpll", AUDPLL_ROOT),
+ CLK_GATE_PARENT("audpll", AUDPLL_ROOT, "osc_24m"),
CLK_GATE("mu2", MU2_ROOT),
CLK_GATE("mu3", MU3_ROOT),
CLK_PDM,
--
2.34.1